gpu.txt (52308B)
1 =========================================================================== 2 GPU information. 3 =========================================================================== 4 About this document. 5 --------------------------------------------------------------------------- 6 This document is a collection of all info on the GPU i could find and my 7 own notes. Most of this is the result of experiment, so not all info might 8 be correct. This document is most probably not complete, and not all 9 capabilities and quirks of the GPU are documented. No responsibility is 10 taken for anything that might occur using the information in this document. 11 12 The K-communications text and the one by Nagra/Blackbag are the basis of 13 this document. 14 15 Notations and conventions 16 When the format of data is given it's shown as a bitwise representation 17 like this: 18 19 pixel| | 20 bit |0f|0e 0d 0c 0b 0a|09 08 07 06 05|04 03 02 01 00| 21 desc.|S |Blue |Green |Red | 22 23 The "pixel" row shows how large the data is in the frame buffer. Each mark 24 one this line denotes the size of the data in frame buffer pixels, as that 25 is the mininum size that kind be addressed. 26 The bit row shows which bits of the data are used, and separators are used 27 to show where the different elements of the data stop and start. MSB is on 28 the left, LSB is on the right. Stuff like |0f-08| means bit $0f to bit $08. 29 The desc. row shows the description of the different elements. With 30 separators where the element starts and ends. 31 32 -------------------------------------------------------------------------- 33 The Graphics Processing Unit (GPU) - overview. 34 -------------------------------------------------------------------------- 35 The GPU is the unit responsible for the graphical output of the PSX. It 36 handles display and drawing of all graphics. It has the control over an 1MB 37 frame buffer and contains a 2Kb texture cache. It has a command and 38 data port. It has a 64 byte command FIFO buffer, which can hold up to 39 3 commands and is connected to a DMA channel for transfer of image data and 40 linked command lists and a DMA channel for reverse clearing an OT. 41 42 --------------------------------------------------------------------------- 43 The Frame Buffer. 44 --------------------------------------------------------------------------- 45 The frame buffer is the memory which stores all grpahic data which the GPU 46 can access and manipulate, while drawing and displaying an image . The 47 memory is under the GPU and cannot be accessed by the CPU directly. It is 48 operated solely by the GPU. The frame buffer has a size of 1 MB and is 49 treated as a space of 1024 pixels wide and 512 pixels high. Each "pixel" 50 has the size of one word (16 bit). It is not treated linearly like usual 51 memory, but is accessed through coordinates, with an upperleft corner of 52 (0,0) and a lower right corner of (1023,511). 53 54 When data is displayed from the frame buffer, a rectangular area is read 55 from the specified coordinate within this memory. The size of this area can 56 be chosen from several hardware defined types. Note that these hardware 57 sizes are only valid when the X and Y stop/start registers are at their 58 default values. This display area can be displayed in two color formats, 59 being 15bit direct and 24bit direct. The data format of one pixel is as 60 follows: 61 62 15bitDirect display. 63 64 pixel| | 65 bit |0f|0e 0d 0c 0b 0a|09 08 07 06 05|04 03 02 01 00| 66 desc.|M |Blue |Green |Red | 67 68 This means each color has a value of 0-31. The MSB of a pixel (M) is used 69 to mask the pixel. 70 71 24bit Direct Display. 72 73 The GPU can also be set to 24bit mode, in which case 3 bytes form one 74 pixel, 1 byte for each color. Data in this mode is arranged as follows: 75 76 pixel|0 |1 |2 | 77 Bit |F-8|7-0|F-8|7-0|F-8|7-0| 78 desc.|G0 |R0 |R1 |B0 |B1 |G1 | 79 80 Thus 2 display pixels are encoded in 3 frame buffer pixels. They are 81 displayed as follows: [R0,G0,B0] [R1,G1,B1] 82 83 --------------------------------------------------------------------------- 84 Primitives. 85 --------------------------------------------------------------------------- 86 A basic firgure which the GPU can draw is called a primitive, and it can 87 draw the following: 88 89 * Polygon 90 The GPU can draw 3 point and 4 point polygons. Each point of the polygon 91 specifies a point in the frame buffer. The polygon can be gouroud shaded. 92 The correct order of vertices for 4 point polygons is as follows: 93 94 1--2 Note: A 4 point polygon is processed internally as two 3 point 95 | | polygons. 96 3--4 Note: When drawing a polygon the GPU will not draw the right 97 most and bottom edge. So a (0,0)-(32,32) rectangle will actually 98 be drawn as (0,0)-(31,31). Make sure adjoining polygons have the same 99 coordinates if you want them to touch eachother!. Haven't checked how this 100 works with 3 point polygons. 101 102 * Polygon with texture 103 A primitive of this type is the same as above, except that a texture is 104 applied. Each vertex of the polygon maps to a point on a texture page in 105 the frame buffer. The polygon can be gouroud shaded. 106 107 Note: Because a 4 point polygon is processed internally as two 3 point 108 polygons, texture mapping is also done independently for both halfs. 109 This has some annoying consequences. 110 111 * Rectangle 112 A rectangle is defined by the location of the top left corner and its width 113 and height. Width and height can be either free, 8*8 or 16*16. It's drawn 114 much faster than a polygon, but gouroud shading is not possible. 115 116 * Sprite 117 A sprite is a textured rectangle, defined as a rectangle with coordinates 118 on a texture page. Like the rectangle is drawn much faster than the polygon 119 equivalent. No gouroud shading possible. 120 121 Note: Even though the primitive is called a sprite, it has nothing in 122 common with the traditional sprite, other than that it's a rectangular 123 piece of graphics. Unlike the psx sprite, the traditional sprite is NOT 124 drawn to the bitmap, but gets sent to the screen instead of the actual 125 graphics data at that location at display time. 126 127 * Line 128 A line is a straight line between 2 specified points. The line can be 129 gouroud shaded. A special form is the polyline, for which an arbitrary 130 number of points can be specified. 131 132 * Dot 133 The dot primitive draws one pixel at the specified coordinate and in the 134 specified color. It is actually a special form of rectangle, with a size 135 of 1*1. 136 137 --------------------------------------------------------------------------- 138 Texture 139 --------------------------------------------------------------------------- 140 A texture is an image put on a polygon or sprite. It is necessary to 141 prepare the data beforehand in the frame buffer. This image is called a 142 texture pattern. The texture pattern is located on a texture page which 143 has a standard size and is located somewhere in the frame buffer, see 144 below. The data of a texture can be stored in 3 different modes: 145 146 * 15bitDirect mode. 147 148 bit |0f|0e 0d 0c 0b 0a|09 08 07 06 05|04 03 02 01 00| 149 desc.|S |Blue |Green |Red | 150 151 This means each color has a value of 0-31. The MSB of a pixel (S)is used 152 to specify it the pixel is semi transparent or not. More on that later. 153 154 155 * 8bit CLUT mode, 156 Each pixel is defined by 8bits and the value of the pixel is converted to 157 a 15bit color using the CLUT(color lookup table) much like standard vga 158 pictures. So in effect you have 256 colors which are in 15bit precision. 159 160 Bit: |0F-08|07-00| 161 desc:|I1 |I0 | 162 163 I0 is the index to the CLUT for the left pixel, I1 for the right. 164 165 * 4bitCLUT mode, 166 Same as above except that only 16 colors can be used. Data is arranged as 167 follows: 168 169 Bit |F-C|B-8|7-4|3-0| 170 desc. |I3 |I2 |I1 |I0 | 171 0 is drawn to the left 172 173 174 * Texture Pages 175 176 Texture pages have a unit size of 256*256 pixels, regardless of colormode. 177 This means that in the frame buffer they will be 64 pixels wide for 4bit 178 CLUT, 128 pixels wide for 8bit CLUT and 256 pixels wide for 15bit direct. 179 The pixels are addressed with coordinates relative to the location of the 180 texture page, not the framebuffer. So the topleft texture coordinate on 181 a texture page is (0,0) and the bottom right one is (255,255) 182 The pages can be located in the frame buffer on X multiples of 64 and Y 183 multiples of 256. More than one texture page can be set up, but each 184 primitive can only contain texture from one page. 185 186 * Texture Windows 187 The area within a texture window is repeated throughout the texture 188 page. The data is not actually stored all over the texture page but 189 the GPU reads the repeated patterns as if they were there. The X and Y 190 and H and W must be multiples of 8. 191 192 * CLUT (Color Lookup Table) 193 The clut is a the table where the colors are stored for the image data in 194 the CLUT modes. The pixels of those images are used as indexes to this 195 table. The clut is arranged in the frame buffer as a 256x1 image for the 196 8bit clut mode, and a 16x1 image for the 4bit clut mode. Each pixel as a 16 197 bit value, the first 15 used of a 15 bit color, and the 16th used for 198 semitransparency. The clut data can be arranged in the frame buffer at X 199 multiples of 16 (X=0,16,32,48,etc) and anywhere in the Y range of 0-511. 200 More than one clut can be prepared but only one can be used for each 201 primitive. 202 203 * Texture Caching 204 205 If polygons with texture are displayed, the GPU needs to read these from 206 the frame buffer. This slows down the drawing process, and as a result 207 the number of polygons that can be drawn in a given timespan. To speed up 208 this process the GPU is equipped with a texture cache, so a given piece 209 of texture needs not to be read multiple times in succession. 210 The texture cache size depends on the color mode used for the textures. 211 In 4 bit CLUT mode it has a size of 64x64, in 8 bit CLUT it's 32x64 and in 212 15bitDirect is 32x32. A general speed up can be achieved by setting up 213 textures according to these sizes. For further speed gain a more precise 214 knowledge of how the cache works is necessary. 215 216 - Cache blocks 217 218 The texture page is divided into non-overlapping cache blocks, each of a 219 unit size according to color mode. These cache blocks are tiled within 220 the texture page. 221 222 +-----+-----+-----+-- 223 |cache| | | 224 |block| | 225 | 0| 1 | 2 .. 226 +-----+-----+-- 227 | | | 228 229 .. 230 231 - Cache entries 232 233 Each cache block is divided into 256 cache entries, which are numbered 234 sequentially, and are 8 bytes wide. So a cache entry holds 16 4bit clut 235 pixels 8 8bit clut pixels, or 4 15bitdirect pixels. 236 237 4bit and 8bit clut: 15bitdirect: 238 +----+----+----+----+ +----+----+----+----+----+----+----+----+ 239 | 0| 1| 2| 3| | 0| 1| 2| 3| 4| 5| 6| 7| 240 +----+----+----+----+ +----+----+----+----+----+----+----+----+ 241 | 4| 5| 6| 7| | 8| 9| a| b| c| d| e| f| 242 +----+----+----+----+ +----+----+----+----+----+----+----+----+ 243 | 8| 9| .. | 10| 11| .. 244 +----+----+-- +----+----+-- 245 | c| ..| | 18| ..| 246 +----+-- +----+-- 247 | .. | .. 248 249 250 The cache can hold only one cache entry by the same number, so if f.e. a 251 piece of texture spans multiple cache blocks and it has data on entry 9 if 252 block 1, but also on entry 9 of block 2, these cannot be in the cache at 253 once. 254 255 256 --------------------------------------------------------------------------- 257 Rendering options. 258 --------------------------------------------------------------------------- 259 There are 3 modes which affect the way the GPU renders the primitives to 260 the frame buffer. 261 262 * Semi Transparency 263 When semi transparency is set for a pixel, the GPU first reads the pixel it 264 wants to write to, and then calculates the color it will write from the 2 265 pixels according to the semitransparency mode selected. Processing speed is 266 lower in this mode because additional reading and calculating are 267 necessary. There are 4 semitransparency modes in the GPU. 268 269 B= the pixel read from the image in the frame buffer, F = the 270 halftransparent pixel 271 272 * 0.5 x B + 0.5 x F 273 * 1.0 x B + 1.0 x F 274 * 1.0 x B - 1.0 x F 275 * 1.0 x B +0.25 x F 276 277 A new semi transparency mode can be set for each primitive. For primitives 278 without texture semi transparency can be selected. For primitives with 279 texture semi transparency is stored in the MSB of each pixel, so some pixels 280 can be set to STP others can be drawn opaque. For the CLUT modes the STP bit 281 is obtained from the CLUT. So if a color index points to a color in the 282 CLUT with the MSB set, it will be drawn semi transparent. 283 284 When the color is black(BGR=0), STP is processed different from when it's not 285 black (BGR<>0). The table below shows the differences: 286 287 transparency proccessing (bit 1 of command packet) 288 BGR STP off on 289 0,0,0 0 Transparent Transparent 290 0,0,0 1 Non-transparent Non-Transparent 291 x,x,x 0 Non-Transparent Non-Transparent 292 x,x,x 1 Non-Transparent Transparent 293 294 * Shading 295 The GPU has a shading function, which will scale the color of a primitive 296 to a specified brightness. There are 2 shading modes: Flat shading, and 297 gouraud shading. Flat shading is the mode in which one brightness value is 298 specified for the entire primitive. In Gouraud shading mode, a different 299 brightness value can be given for each vertex of a primitive, and the 300 brightness between these points is automatically interpolated. 301 302 * Mask 303 304 The mask function will prevent to GPU to write to specific pixels when 305 drawing in the framebuffer. This means that when the gpu is drawing a 306 primitive to a masked area, it will first read the pixel at the coordinate 307 it wants to write to, check if it's masking bit is set, and if so refrain 308 from writing to that particular pixel. The masking bit is the MSB of the 309 pixel, just like the STP bit. 310 To set this masking bit, the GPU provides a mask out mode, which will set 311 the MSB of any pixel it writes. If both mask out and mask evaluation are 312 on, the GPU will not draw to pixels with set MSB's, and will draw pixels 313 with set MSB's to the others, these in turn becoming masked pixels. 314 315 --------------------------------------------------------------------------- 316 Drawing Environment 317 --------------------------------------------------------------------------- 318 The drawing environment specifies all global parameters the GPU needs for 319 drawing primitives. 320 321 * Drawing offset. 322 This locates the top left corner of the drawing area. Coordinates of 323 primitives originate to this point. So if the drawing offset is (0,240) 324 and a vertex of a poligon is located at (16,20) it will be drawn to the 325 frame buffer at (0+16,240+20). 326 327 * Drawing clip area 328 This specifies the maximum range the GPU draws primitives to. So in effect 329 it specifies the top left and bottom right corner of the drawing area. 330 331 * Dither enable 332 When dither is enabled the GPU will dither areas during shading. It will 333 process internally in 24 bit and ditter the colors when converting back to 334 15bit. When it is off, the lower 3 bits of each color simply get 335 discarded. 336 337 * Draw to display enable. 338 This will enable/disable any drawing to the area that is currently 339 displayed. 340 341 * Mask enable 342 When turned on any pixel drawn to the framebuffer by the GPU will have a 343 set masking bit. (= set MSB) 344 345 * Mask judgement enable 346 Specifies if the mask data from the frame buffer is evaluated at the time 347 of drawing. 348 349 --------------------------------------------------------------------------- 350 Display Environment. 351 --------------------------------------------------------------------------- 352 This contains all information about the display, and the area displayed. 353 354 * Display area in frame buffer 355 This specifies the resolution of the display. The size can be set 356 as follows: 357 358 Width: 256,320,384,512 or 640 pixels 359 Height: 240 or 480 pixels 360 361 These sizes are only an indication on how many pixels will be displayed 362 using a default start end. These settings only specify the resolution of 363 the display. 364 365 * Display start/end. 366 Specifies where the display area is positioned on the screen, and how 367 much data gets sent to the screen. The screen sizes of the display area 368 are valid only if the horizontal/vertical start/end values are default. By 369 changing these you can get bigger/smaller display screens. On most TV's 370 there is some black around the edge, which can be utilised by setting the 371 start of the screen earlier and the end later. The size of the pixels is 372 NOT changed with these settings, the GPU simply sends more data to the 373 screen. Some monitors/TVs have a smaller display area and the extended 374 size might not be visible on those sets.(Mine is capable of about 330 375 pixels horizontal, and 272 vertical in 320*240 mode) 376 377 378 * Interlace enable 379 380 When enabled the GPU will display the even and odd lines of the display 381 area alternately. It is necessary to set this when using 480 lines as the 382 number of scan lines on a TV screen are not sufficient to display 480 383 lines. 384 385 * 15bit/24bit direct display 386 Switches between 15bit/24bit display mode. 387 388 * Video mode 389 Selects which video mode to use, which are either PAL or NTSC. 390 391 -------------------------------------------------------------------------- 392 Communication and OT's. 393 -------------------------------------------------------------------------- 394 All data regarding drawing and drawing environment are sent as packets to 395 the GPU. Each packet tells the GPU how and where to draw one primitive, or 396 it sets one of the drawing environment parameters. The display environment 397 is set up through single word commands using the control port of the GPU. 398 399 Packets can be forwarded word by word through the data port of the GPU, or 400 more efficiently for large numbers of packets through DMA. A special DMA 401 mode was created for this so large numbers of packets can be sent and 402 managed easily. In this mode a list of packets is sent, where each entry in 403 the list contains a header which is one word containing the address of the 404 next entry and the size of the packet and the packet itself. A result of 405 this is that the packets do not need to be stored sequentially. This makes 406 it possible to easily control the order in which packets get processed. The 407 GPU processes the packets it gets in the order they are offered. So the 408 first entry in the list also gets drawn first. To insert a packet into the 409 middle of the list simply find the packet after which you want it to be 410 processed, replace the address in that packet with the address of the new 411 packet, and let that point to the address you replaced. 412 413 To aid you in finding a location in the list the Ordering Table was 414 invented. At first this is basically a linked list with entries of packet 415 size 0, so it's a list of only listentryheaders, where each entry points to 416 to the next entry. Then as primitives are generated by your program you can 417 then add them to the table at a certain index. Just read the address in the 418 table entry and replace it with the address of the new packet and store the 419 address from the table in the packet. When all packets are generated and 420 you want to draw, just pass the address of the first listentry to the DMA 421 and the packets will get drawn in the order you entered the packets to the 422 table. Packets entered at a higher table index will get drawn after those 423 entered at a lower table index. Packets entered at the same index will get 424 drawn in the order they were entered, the last one first. 425 426 In 3d drawing it's most common that you want the primitives with the highest 427 Z value to be drawn first, so it would be nice if the table would be drawn 428 the other way around, so the Z value can be used as index. This is a simple 429 thing, just make a table of which each entry points to the previous entry, 430 and start the DMA with the address of the last table entry. To assist you 431 in making such a table, a special DMA channel is available which creates 432 it for you. 433 434 -------------------------------------------------------------------------- 435 GPU operation 436 -------------------------------------------------------------------------- 437 * GPU control registers. 438 There are 2 32 bit io ports for the GPU, which are: 439 440 $1f801810 GPU Data 441 $1f801814 GPU control/Status 442 443 The data register is used to exchange data with the GPU. 444 The control/status register, gives the status of the GPU when read, and 445 sets the control bits when written to. 446 447 * Control/Status Register $1f801814 448 449 Status (Read) 450 ----------------------------------------------------------------------------- 451 |1f |1e 1d|1c |1b |1a |19 18|17 |16 |15 |14 |13 |12 11 |10 | 452 |lcf|dma |com|img|busy| ? ?|den|isinter|isrgb24|Video|Height|Width0|Width1| 453 ----------------------------------------------------------------------------- 454 455 W0 W1 456 Width: 00 0 256 pixels 457 01 0 320 458 10 0 512 459 11 0 640 460 00 1 384 461 Height: 0 240 pixels 462 1 480 463 Video: 0 NTSC 464 1 PAL 465 isrgb24: 0 15 bit direct mode 466 1 24 bit direct mode 467 isinter: 0 Interlace off 468 1 Interlace on 469 den: 0 Display enabled 470 1 Display disabled 471 busy: 0 GPU is Busy (ie. drawing primitives) 472 1 GPU is Idle 473 img: 0 Not Ready to send image (packet $c0) 474 1 Ready 475 com: 0 Not Ready to recieve commands 476 1 Ready 477 dma: 00 DMA off, communication through GP0 478 01 479 10 DMA CPU -> GPU 480 11 DMA GPU -> CPU 481 482 483 lcf: 0 Drawing even lines in interlace mode 484 1 Drawing uneven lines in interlace mode 485 ---------------------------------------------------- 486 |0f 0e 0d|0c|0b|0a |09 |08 07|06 05|04|03 02 01 00| 487 | ? ? ?|me|md|dfe |dtd|tp |abr |ty|tx | 488 ---------------------------------------------------- 489 490 tx: 0 0 Texture page X = tx*64 491 1 64 492 2 128 493 3 196 494 4 ... 495 ty 0 0 Texture page Y 496 1 256 497 abr %00 0.5xB+0.5 xF Semi transparent state 498 %01 1.0xB+1.0 xF 499 %10 1.0xB-1.0 xF 500 %11 1.0xB+0.25xF 501 tp %00 4bit CLUT Texture page color mode 502 %01 8bit CLUT 503 %10 15bit 504 dtd 0 Ditter off 505 1 Ditter on 506 dfe 0 Draw to display area prohibited 507 1 Draw to display area allowed 508 md 0 off 509 1 on Apply mask bit to drawn pixels. 510 me 0 off 511 1 on No drawing to pixels with set mask bit. 512 513 Control (Write) 514 -------------------------------------------------------------------------- 515 A control command is composed of one word as follows: 516 517 bit 1f-18 17-0 518 command parameter. 519 520 The composition of the parameter is different for each command. 521 522 -------------------------------------------------------------------------- 523 *Reset GPU 524 command $00 525 parameter $000000 526 Description Resets the GPU. Also seems to turn off screen. 527 (sets status to $14802000) 528 -------------------------------------------------------------------------- 529 *Reset Command Buffer 530 command $01 531 parameter $000000 532 Description Resets the command buffer. 533 534 -------------------------------------------------------------------------- 535 *Reset IRQ 536 command $02 537 parameter $000000 538 Description Resets the IRQ. No idea of what this means. 539 540 -------------------------------------------------------------------------- 541 *Display Enable 542 command $03 543 parameter $000000 Display enable 544 $000001 Display disable 545 Description Turns on/off display. Note that a turned off 546 screen still gives the flicker of NTSC on a 547 pal screen if NTSC mode is selected.. 548 -------------------------------------------------------------------------- 549 *DMA setup. 550 command $04 551 parameter $000000 DMA disabled 552 $000001 DMA ? 553 $000002 DMA CPU to GPU 554 $000003 DMA GPU to CPU 555 Description Sets dma direction. K-comm also mentions something 556 about parameter $01, but i wasn't able to translate. 557 -------------------------------------------------------------------------- 558 *Start of display area 559 command $05 560 parameter bit $00-$09 X (0-1023) 561 bit $0A-$12 Y (0-512) 562 = Y<<10 + X 563 description Locates the top left corner of the display area. 564 -------------------------------------------------------------------------- 565 *Horizontal Display range 566 command $06 567 parameter bit $00-$0b X1 ($1f4-$CDA) 568 bit $0c-$17 X2 569 = X1+X2<<12 570 description Specifies the horizontal range within which the 571 display area is displayed. The display is relative 572 to the display start, so X coordinate 0 will be at 573 the value in X1. The display end is not relative to 574 the display start. The number of pixels that get sent 575 to the screen in 320 mode are (X2-X1)/8. How many 576 actually are visible depends on your TV/monitor. 577 (normally $260-$c56) 578 -------------------------------------------------------------------------- 579 *Vertical Display range 580 command $07 581 parameter bit $00-$09 Y1 582 bit $0a-$14 Y2 583 = Y1+Y2<<10 584 description Specifies the vertical range within which the 585 display area is displayed. The display is relative 586 to the display start, so Y coordinate 0 will be at 587 the value in Y1. The display end is not relative to 588 the display start. The number of pixels that get sent 589 to the display are Y2-Y1, in 240 mode. 590 (Not sure about the default values, should be 591 something like NTSC $010-$100, PAL $023-$123) 592 -------------------------------------------------------------------------- 593 *Display mode 594 command $08 595 parameter bit $00-$01 Width 0 596 bit $02 Height 597 bit $03 Videomode See above 598 bit $04 Isrgb24 599 bit $05 Isinter 600 bit $06 Width1 601 bit $07 Reverseflag 602 603 description Sets the display mode. 604 -------------------------------------------------------------------------- 605 *GPU Info 606 command $10 607 parameter $000000 608 $000001 609 $000002 610 $000003 Draw area top left 611 $000004 Draw area bottom right 612 $000005 Draw offset 613 $000006 614 $000007 GPU Type, should return 2 for a standard GPU. 615 616 description Returns requested info. Read result from GP0. 617 0,1 seem to return draw area top left also 618 6 seems to return draw offset too. 619 620 -------------------------------------------------------------------------- 621 *Some other commands i do not know the function of: 622 623 *????? 624 command $20 625 parameter ??????? 626 description i've seen it used with value $000504 627 what it does????? 628 629 *????? 630 command $09 631 parameter $000001 ?? 632 description I've seen it used with value $000001 633 what it does????? 634 635 -------------------------------------------------------------------------- 636 Command Packets, Data Register. 637 -------------------------------------------------------------------------- 638 Primitive command packets use an 8 bit command value which is present in 639 all packets. They contain a 3 bit type block and a 5 bit option block of 640 which the meaning of the bits depend on the type. Layout is as follows: 641 642 Type: 643 000 GPU command 644 001 Polygon primitive 645 010 Line primitive 646 011 Sprite primitive 647 100 Transfer command 648 111 Environment command 649 650 Configuration of the option blocks for the primitives is as follows: 651 652 Polygon: 653 | 7 6 5 | 4 | 3 | 2 | 1 | 0 | 654 | 0 0 1 |IIP|3/4|Tme|Abe|Tge| 655 656 Line: 657 | 7 6 5 | 4 | 3 | 2 | 1 | 0 | 658 | 0 1 0 |IIP|Pll| 0 |Abe| 0 | 659 660 Sprite: 661 | 7 6 5 | 4 3 | 2 | 1 | 0 | 662 | 1 0 0 | Size |Tme|Abe| 0 | 663 664 665 IIP 0 Flat Shading 666 1 Gouroud Shading 667 3/4 0 3 vertex polygon 668 1 4 vertex polygon 669 Tme 0 Texture mapping off 670 1 on 671 Abe 0 Semi transparency off 672 1 on 673 Tge 0 Brightness calculation at time of texture mapping on 674 1 off. (draw texture as is) 675 Size 00 Free size (Specified by W/H) 676 01 1 x 1 677 10 8 x 8 678 11 16 x 16 679 Pll 0 Single line (2 vertices) 680 1 Polyline (n vertices) 681 682 * Color information 683 Color information is forwarded as 24 bit data. It is parsed to 684 15 bit by the GPU. 685 686 Layout as follows: 687 688 17-10 $0f-$08 $07-$00 689 Blue Green Red 690 691 * Shading information. 692 For textured primitive shading data is forwarded by this packet. 693 Layout is the same as for color data, the RGB values controlling 694 the brightness of the individual colors ($00-$7f). A value of $80 in a 695 color will take the former value as data. 696 697 *Texture Page information 698 The Data is 16 bit wide, layout is as follows: 699 700 |F E D C B A 9|8 7|6 5|4 |3 2 1 0| 701 |0 |tp |abr|ty|tx | 702 703 tx 0-f X*64 texture page x coord 704 ty 0 0 texture page y coord 705 1 256 706 abr 0 0.5xB+0.5 xF Semi transparency mode 707 1 1.0xB+1.0 xF 708 2 1.0xB-1.0 xF 709 3 1.0xB+0.25xF 710 tp 0 4bit CLUT 711 1 8bit CLUT 712 2 15bit direct 713 714 CLUT-ID 715 Specifies the location of the CLUT data. Data is 16bits. 716 717 F-6 Y coordinate 0-511 718 5-0 X coordinate X/16 719 720 -------------------------------------------------------------------------- 721 abbreviations in packet list 722 -------------------------------------------------------------------------- 723 BGR Color/Shading info see above. 724 xn,yn 16 bit values of X and Y in frame buffer. 725 un,vn 8 bit values of X and Y in texture page 726 tpage texture page information packet, see above 727 clut clut ID, see above. 728 729 -------------------------------------------------------------------------- 730 Packet list. 731 -------------------------------------------------------------------------- 732 The packets sent to the GPU are processed as a group of data, 733 each one word wide. The data must be written to the GPU data register 734 ($1f801810) sequentially. Once all data has been recieved, the GPU 735 starts operation. 736 737 Overview of packet commands: 738 739 Primitive drawing packets 740 $20 monochrome 3 point polygon 741 $24 textured 3 point polygon 742 $28 monchrome 4 point polygon 743 $2c textured 4 point polygon 744 $30 gradated 3 point polygon 745 $34 gradated textured 3 point polygon 746 $38 gradated 4 point polygon 747 $3c gradated textured 4 point polygon 748 $40 monochrome line 749 $48 monochrome polyline 750 $50 gradated line 751 $58 gradated line polyline 752 $60 rectangle 753 $64 sprite 754 $68 dot 755 $70 8*8 rectangle 756 $74 8*8 sprite 757 $78 16*16 rectangle 758 $7c 16*16 sprite 759 GPU command & Transfer packets 760 $01 clear cache 761 $02 frame buffer rectangle draw 762 $80 move image in frame buffer 763 $a0 send image to frame buffer 764 $c0 copy image from frame buffer 765 Draw mode/environment setting packets 766 $e1 draw mode setting 767 $e2 texture window setting 768 $e3 set drawing area top left 769 $e4 set drawing area bottom right 770 $e5 drawing offset 771 $e6 mask setting 772 773 -------------------------------------------------------------------------- 774 Packet Descriptions 775 -------------------------------------------------------------------------- 776 Primitive Packets 777 -------------------------------------------------------------------------- 778 $20 monochrome 3 point polygon 779 780 |1f-18|17-10|0f-08|07-00| 781 1|$20 |BGR |command+color 782 2|y0 |x0 |vertexes 783 3|y1 |x1 | 784 4|y2 |x2 | 785 -------------------------------------------------------------------------- 786 $24 textured 3 point polygon 787 |1f-18|17-10|0f-08|07-00| 788 1|$24 |BGR |command+color 789 2|y0 |x0 |vertex 0 790 3|clut |v0 |u0 |clutid+ texture coords vertext 0 791 4|y1 |x1 | 792 5|tpage |v1 |u1 | 793 6|y2 |x2 | 794 7| |v2 |u2 | 795 -------------------------------------------------------------------------- 796 $28 monchrome 4 point polygon 797 |1f-18|17-10|0f-08|07-00| 798 1|$28 |BGR |command+color 799 2|y0 |x0 |vertexes 800 3|y1 |x1 | 801 4|y2 |x2 | 802 5|y3 |x3 | 803 -------------------------------------------------------------------------- 804 $2c textured 4 point polygon 805 |1f-18|17-10|0f-08|07-00| 806 1|$2c |BGR |command+color 807 2|y0 |x0 |vertex 0 808 3|clut |v0 |u0 |clutid+ texture coords vertext 0 809 4|y1 |x1 | 810 5|tpage |v1 |u1 | 811 6|y2 |x2 | 812 7| |v2 |u2 | 813 8|y3 |x3 | 814 9| |v3 |u3 | 815 -------------------------------------------------------------------------- 816 $30 graduation 3 point polygon 817 |1f-18|17-10|0f-08|07-00| 818 1|$30 |BGR0 |command+color 819 2|y0 |x0 |vertexes 820 3| |BGR1 | 821 4|y1 |x1 | 822 5| |BGR2 | 823 6|y2 |x2 | 824 -------------------------------------------------------------------------- 825 $34 shaded textured 3 point polygon 826 |1f-18|17-10|0f-08|07-00| 827 1|$34 |BGR0 |command+color 828 2|y0 |x0 |vertex 0 829 3|clut |v0 |u0 |clutid+ texture coords vertex 0 830 4| |BGR1 | 831 5|y1 |x1 | 832 6|tpage |v1 |u1 | 833 7| |BGR2 | 834 8|y2 |x2 | 835 9| |v2 |u2 | 836 -------------------------------------------------------------------------- 837 $38 gradated 4 point polygon 838 |1f-18|17-10|0f-08|07-00| 839 1|$38 |BGR0 |command+color 840 2|y0 |x0 |vertexes 841 3| |BGR1 | 842 4|y1 |x1 | 843 5| |BGR2 | 844 6|y2 |x2 | 845 7| |BGR3 | 846 8|y3 |x3 | 847 -------------------------------------------------------------------------- 848 $3c shaded textured 4 point polygon 849 |1f-18|17-10|0f-08|07-00| 850 1|$3c |BGR0 |command+color 851 2|y0 |x0 |vertex 0 852 3|clut |v0 |u0 |clutid+ texture coords vertex 0 853 4| |BGR1 | 854 5|y1 |x1 | 855 6|tpage |v1 |u1 |texture page location 856 7| |BGR2 | 857 8|y2 |x2 | 858 9| |v2 |u2 | 859 a| |BGR3 | 860 b|y3 |x3 | 861 c| |v3 |u3 | 862 -------------------------------------------------------------------------- 863 $40 monochrome line 864 |1f-18|17-10|0f-08|07-00| 865 1|$40 |BGR |command+color 866 2|y0 |x0 |vertex 0 867 3|y1 |x1 |vertex 1 868 -------------------------------------------------------------------------- 869 $48 single color polyline 870 |1f-18|17-10|0f-08|07-00| 871 1|$48 |BGR |command+color 872 2|y0 |x0 |vertex 0 873 3|y1 |x1 |vertex 1 874 4|y2 |x2 |vertex 2 875 876 .|yn |xn |vertex n 877 .|$55555555 Temination code. 878 879 Any number of points can be entered, end with termination code. 880 -------------------------------------------------------------------------- 881 $50 gradated line 882 |1f-18|17-10|0f-08|07-00| 883 1|$50 |BGR0 |command+color 884 2|y0 |x0 | 885 3| |BGR1 | 886 4|y1 |x1 | 887 -------------------------------------------------------------------------- 888 $58 gradated line polyline 889 |1f-18|17-10|0f-08|07-00| 890 1|$58 |BGR0 |command+color 891 2|y0 |x0 | 892 3| |BGR1 | 893 4|y1 |x1 | 894 5| |BGR2 | 895 6|y2 |x2 | 896 897 .| |BGRn | 898 .|yn |xn | 899 .|$55555555 Temination code. 900 Any number of points can be entered, end with termination code. 901 -------------------------------------------------------------------------- 902 $60 rectangle 903 |1f-18|17-10|0f-08|07-00| 904 1|$60 |BGR |command+color 905 2|y |x | 906 3|h |w | 907 -------------------------------------------------------------------------- 908 $64 sprite 909 |1f-18|17-10|0f-08|07-00| 910 1|$64 |BGR |command+color 911 2|y |x | 912 3|clut |v |u |clut location, texture page y,x 913 4|h |w | 914 -------------------------------------------------------------------------- 915 $68 dot 916 |1f-18|17-10|0f-08|07-00| 917 1|$68 |BGR |command+color 918 2|y |x | 919 -------------------------------------------------------------------------- 920 $70 8*8 rectangle 921 |1f-18|17-10|0f-08|07-00| 922 1|$70 |BGR |command+color 923 2|y |x | 924 -------------------------------------------------------------------------- 925 $74 8*8 sprite 926 |1f-18|17-10|0f-08|07-00| 927 1|$74 |BGR |command+color 928 2|y |x | 929 3|clut |v |u |clut location, texture page y,x 930 -------------------------------------------------------------------------- 931 $78 16*16 rectangle 932 |1f-18|17-10|0f-08|07-00| 933 1|$78 |BGR |command+color 934 2|y |x | 935 -------------------------------------------------------------------------- 936 $7c 16*16 sprite 937 |1f-18|17-10|0f-08|07-00| 938 1|$7c |BGR |command+color 939 2|y |x | 940 3|clut |v |u |clut location, texture page y,x 941 -------------------------------------------------------------------------- 942 GPU command & Transfer packets 943 -------------------------------------------------------------------------- 944 $01 clear cache 945 |1f-18|17-10|0f-08|07-00| 946 1|$01 |0 |clear cache. 947 948 Seems to be the same as the GP1 command. 949 -------------------------------------------------------------------------- 950 $02 frame buffer rectangle draw 951 |1f-18|17-10|0f-08|07-00| 952 1|$02 |BGR |command+color 953 2|Y |X |Topleft corner 954 3|H |W |Width & Height 955 Fills the area in the frame buffer with the value in RGB. This command 956 will draw without regard to drawing environment settings. Coordinates are 957 absolute frame buffer coordinates. Max width is $3ff, max height is $1ff. 958 -------------------------------------------------------------------------- 959 $80 move image in frame buffer 960 |1f-18|17-10|0f-08|07-00| 961 1|$02 | 0|command 962 2|sY |sX |Source coord. 963 3|dY |dX |Destination coord. 964 4|H |W |Height+Width of transfer 965 Copys data within framebuffer 966 -------------------------------------------------------------------------- 967 $01 $a0 send image to frame buffer 968 |1f-18|17-10|0f-08|07-00| 969 |$01 | |Reset command buffer (write to GP1 or GP0) 970 1|$A0 | | 971 2|Y |X |Destination coord. 972 3|H |W |Height+Width of transfer 973 4|pix1 |pix0 |image data 974 5.. 975 ?|pixn |pixn-1 | 976 Transfers data from mainmemory to frame buffer 977 If the number of pixels to be sent is odd, an extra should be 978 sent. (32 bits per packet) 979 --------------------------------------------------------------------------- 980 $01 $c0 copy image from frame buffer 981 |1f-18|17-10|0f-08|07-00| 982 |$01 | |Reset command buffer (write to GP1 or GP0) 983 1|$C0 | | 984 2|Y |X |Destination coord. 985 3|H |W |Height+Width of transfer 986 4|pix1 |pix0 |image data (read from data port) 987 5.. 988 ?|pixn |pixn-1 | 989 Transfers data from frame buffer to mainmemory. Wait for bit 27 990 of the status register to be set before reading the image data. 991 When the number of pixels is odd, an extra pixel is read at the 992 end.(because on packet is 32 bits) 993 -------------------------------------------------------------------------- 994 Draw mode/environment setting packets 995 -------------------------------------------------------------------------- 996 Some of these packets can also be by primitive packets, in any 997 case it is the last packet of either that the GPU recieved 998 that is active. so if a primitive sets tpage info, it will over 999 write the existing data, even if it was sent by an $e? packet. 1000 -------------------------------------------------------------------------- 1001 $e1 draw mode setting 1002 |1f-18|17-0b|0a |09 |08 07|06 05|04|03 02 01 00| 1003 1|$e1 | |dfe|dtd|tp |abr |ty|tx | command +values 1004 1005 see above for explanations 1006 1007 It seems that bit $0b-$0d of the status reg can also be passed with this 1008 command on some GPU's other than type 2. (ie. Command $10000007 doesn't 1009 return 2) 1010 -------------------------------------------------------------------------- 1011 $e2 texture window setting 1012 1013 |1F-18|17-14|13-0F|0E-0A|09-05|04-00| 1014 1|$E2 |twy |twx |twh |tww | command + value 1015 1016 twx Texture window X, (twx*8) 1017 twy Texture window Y, (twy*8) 1018 tww Texture window width, 256-(tww*8) 1019 twh Texture window height, 256-(twh*8) 1020 -------------------------------------------------------------------------- 1021 $e3 set drawing area top left 1022 |1f-18|17-14|13-0a|09-00| 1023 1|$e3 | |Y |X | 1024 sets the drawing area topleft corner. X&Y are absolute frame 1025 buffer coords. 1026 -------------------------------------------------------------------------- 1027 $e4 set drawing area bottom right 1028 |1f-18|17-14|13-0a|09-00| 1029 1|$e4 | |Y |X | 1030 sets the drawing area bottom right. X&Y are absolute frame 1031 buffer coords. 1032 -------------------------------------------------------------------------- 1033 $e5 drawing offset 1034 |1f-18|17-14|14-0b|0a-00| 1035 1|$e5 | |OffsY|OffsX| 1036 (offset Y = y << 11) 1037 sets the drawing area offset within the drawing area. X&Y are 1038 offsets in the frame buffer. 1039 -------------------------------------------------------------------------- 1040 $e6 mask setting 1041 |1f-18|17-02|01 |00 | 1042 1|$e6 | |Mask2|Mask1| 1043 1044 Mask1 Set mask bit while drawing. 1 = on 1045 Mask2 Do not draw to mask areas. 1= on 1046 1047 While mask1 is on, the GPU will set the MSB of all pixels it draws. 1048 While mask2 is on, the GPU will not write to pixels with set MSB's 1049 1050 -------------------------------------------------------------------------- 1051 DMA 1052 -------------------------------------------------------------------------- 1053 The GPU has two DMA channels allocated to it. DMA channel 2 is used to send 1054 linked packet lists to the GPU and to transfer image data to and from the 1055 frame buffer. DMA channel 6 is sets up an empty linked list, of which each 1056 entry points to the previous (ie. reverse clear an OT.) 1057 -------------------------------------------------------------------------- 1058 D2_MADR DMA base address. $1f8010a0 1059 bit |1f 00| 1060 desc|madr | 1061 1062 madr pointer to the adress the DMA will start reading from/writing to 1063 -------------------------------------------------------------------------- 1064 D2_BCR DMA block control $1f8010a4 1065 bit |1f 10|0f 00| 1066 desc|ba |bs | 1067 1068 ba Amount of blocks 1069 bs Blocksize (words) 1070 1071 Sets up the DMA blocks. Once started the DMA will send ba blocks of bs 1072 words. Don't set a blocksize larger then $10 words, as the command buffer 1073 of the GPU is 64 bytes. 1074 -------------------------------------------------------------------------- 1075 D2_CHCR DMA channel control $1f8010a8 1076 bit |1f-19|18|17-0c|0b|0a|09|08|07 01|00| 1077 desc| 0|Tr| 0| 0|Li|Co| 0| 0|Dr| 1078 1079 Tr 0 No DMA transfer busy. 1080 1 Start DMA transfer/DMA transfer busy. 1081 Li 1 Transfer linked list. 1082 Co 1 Transfer continous stream of data. 1083 Dr 0 direction to memory 1084 1 direction to GPU 1085 1086 This configures the DMA channel. The DMA starts when bit 18 is set. DMA 1087 is finished as soon as bit 18 is cleared again. To send or recieve data 1088 to/from VRAM send the appriopriate GPU packets first ($a0/$c0) 1089 -------------------------------------------------------------------------- 1090 D6_MADR DMA base address. $1f8010e0 1091 bit |1f 00| 1092 desc|madr | 1093 1094 madr Last table entry. 1095 -------------------------------------------------------------------------- 1096 D6_BCR DMA block control $1f8010e4 1097 bit |1f 00| 1098 desc|bc | 1099 1100 bc Number of list entries. 1101 -------------------------------------------------------------------------- 1102 D6_CHCR DMA channel control $1f8010e8 1103 bit |1f-1d|1c|1b-19|18|17-02|01|00| 1104 desc| 0|OT| 0|Tr| 0|Ot| 0| 1105 1106 Tr 0 No DMA transfer busy. 1107 1 Start DMA transfer/DMA transfer busy. 1108 Ot 1 Set to do an OT clear. 1109 1110 When this register is set to $11000002, the DMA channel will create an 1111 empty linked list of D6_BCR entries ending at the address in D6_MADR. Each 1112 entry has a size of 0, and points to the previous. The first entry is 1113 So if D6_MADR = $80100010, D6_BCR=$00000004, and the DMA is kicked this 1114 will result in a list looking like this: 1115 $80100000 $00ffffff 1116 $80100004 $00100000 1117 $80100008 $00100004 1118 $8010000c $00100008 1119 $80100010 $0010000c 1120 -------------------------------------------------------------------------- 1121 DPCR Dma control register $1f8010f0 1122 |1f 1c|1b 18|17 14|13 10|0f 0c|0b 08|07 04|03 00| 1123 | |Dma6 |Dma5 |Dma4 |Dma3 |Dma2 |Dma1 |Dma0 | 1124 1125 Each register has a 4 bit control block allocated in this 1126 register. 1127 Bit 3: 1= Dma Enabled 1128 2: ? 1129 1: ? 1130 0: ? 1131 1132 Bit 3 must be set for a channel to operate. 1133 1134 -------------------------------------------------------------------------- 1135 Common GPU functions, step by step. 1136 -------------------------------------------------------------------------- 1137 * Initializing the GPU. 1138 1139 First thing to do when using the GPU is to initialize it. To do that take 1140 the following steps: 1141 1142 1 - Reset the GPU (GP1 command $00). This turns off the display aswell. 1143 2 - Set horizontal and vertical start/end. (GP1 command $06, $07) 1144 3 - Set display mode. (GP1 command $08) 1145 4 - Set display offset. (GP1 command $05) 1146 5 - Set draw mode. (GP0 command $e1) 1147 6 - Set draw area. (GP0 command $e3, $e4) 1148 7 - Set draw offset. (GP0 command $e5) 1149 8 - Enable display. 1150 1151 * Sending a linked list. 1152 1153 The normal way to send large numbers of primitives is by using a linked 1154 list dma transfer. This list is built up of entries of which each points to 1155 the next. One entry looks like this: 1156 1157 dw $nnYYYYYY ; nn = the number of words in the list entry 1158 ; YYYYYY = address of next list entry & $00ffffff 1159 1160 1 dw .. ; here goes the primitive. 1161 2 dw .. ; 1162 . dw .. ; 1163 nn-1 dw .. ; 1164 nn dw .. ; 1165 1166 The last entry in the list should have $ffffff as pointer, which is the 1167 terminator. As soon as this value is found DMA is ended. If the entry 1168 size is set to 0, no data will be transferred to the GPU and the next 1169 entry is processed. 1170 1171 To send the list do this: 1172 1 - Wait for the GPU to be ready to recieve commands. (bit $1c == 1) 1173 2 - Enable DMA channel 2 1174 3 - Set GPU to DMA cpu->gpu mode. ($04000002) 1175 3 - Set D2_MADR to the start of the list 1176 4 - Set D2_BCR to zero. 1177 5 - Set D2_CHCR to link mode, mem->GPU and dma enable. ($01000401) 1178 1179 * Uploading Image data through DMA. 1180 1181 To upload an image to VRAM take the following steps: 1182 1183 1 - Wait for the GPU to be idle and DMA to finish. Enable DMA channel 2 1184 if necessary. 1185 2 - Send the 'Send image to VRAM' primitive. (You can send this through 1186 dma if you want. Use the linked list method described above) 1187 3 - Set DMA to CPU->GPU ($04000002) (if you didn't do so already in the 1188 previous step) 1189 4 - Set D2_MADR to the start of the list 1190 5 - Set D2_BCR with : bits 31-16 = Number of words to send (H*W /2) 1191 bits 15- 0 = Block size of 1 word. ($01) 1192 if H*W is odd, add 1. (Pixels are 2 bytes, send 1193 an extra blank pixel in case of an odd amount) 1194 6 - Set D2_CHCR to continuous mode, mem -> GPU and dma enable. ($01000201) 1195 1196 Note that H, W, X and Y are always in frame buffer pixels, even if you send 1197 image data in other formats. 1198 You can use bigger block sizes if you need more speed. If the number of 1199 words to be sent is not a multiple of the blocksize, you'll have to send 1200 the remainder seperately, because the GPU only accepts an extra halfword 1201 if the number of pixels is odd. (ie. of the last word sent, only the low 1202 half word is used.) Also take care not to use blocksizes bigger than $10, as 1203 the buffer of the GPU is only 64 bytes (=$10 words). 1204 1205 * Waiting to send commands 1206 1207 You can send new commands as soon as DMA has ceased and the GPU is ready. 1208 1 - Wait for bit $18 to become 0 in D2_CHCR 1209 2 - Wait for bit $1c to become 1 in GP1. 1210 1211 * Vsync 1212 1213 Step by step for a VSYNC counter coming up (not)soon. 1214 1215 Meanwhile you can init the pad driver and as soon as you want to 1216 check for VSYNC, fill the return buffer with 0 and wait for it to change. 1217 The pad driver checks the pads every VSYNC. Check the greentro source for 1218 an example. 1219 1220 -------------------------------------------------------------------------- 1221 Missing info. 1222 -------------------------------------------------------------------------- 1223 There's still a lot yet uncovered, so if you have/know anything that's not 1224 in here please mail it to me. Things i'm looking for particularly are 1225 info on the differences between the various versions and revisions of the 1226 GPU, and something about drawing speeds and other timing. 1227 1228 -------------------------------------------------------------------------- 1229 History: 1230 -------------------------------------------------------------------------- 1231 23/apr/1999 First public release. 1232 28/apr/1999 Some bugfixes and rewrites. 1233 Info on texture pages corrected. <Silpheed> 1234 8/may/1999 Detailed packet composition. 1235 20/may/1999 DMA & Step by steps added. 1236 25/jun/1999 More DMA, OT and lists. 1237 30/aug/1999 Correction. ($03) 1238 -------------------------------------------------------------------------- 1239 Maintained by doomed/padua. Any errors, additions -> <doomed@c64.org> 1240 -------------------------------------------------------------------------- 1241 --== http://psx.rules.org/ ==-- 1242 --== http://www.padua.org/ ==-- 1243 -------------------------------------------------------------------------- 1244 Thanx & Hello to: 1245 Silpheed Groepaz Brainwalker & Hitmen, Antiloop Middy Danzig & Napalm, 1246 K-Communications, Blackbag, TDJ Sander & Focus, Burglar LCF & SCS*TRC, 1247 Deekay & Crest, Graham NO-XS & Oxyron, MrAlpha Fungus & F4CG, Zealot & 1248 Wrath Design, Shape, Naphalm Jazzcat & Onslaught, Reyn Ouwehand, WHW & WOW, 1249 all active people on PSX and C64, #psxdev, #c-64. 1250 --------------------------------------------------------------------------