system.txt (35546B)
1 -------------------------------------------------------------------------- 2 System Operation 3 -------------------------------------------------------------------------- 4 5 Introduction 6 -------------------------------------------------------------------------- 7 This text covers the usage of the R3000, the system control coprocessor and 8 hardware registers, the file server and some system calls. 9 10 -------------------------------------------------------------------------- 11 R3000 12 -------------------------------------------------------------------------- 13 The heart of the psx is a MIPS R3000. The version in the PSX has two 14 coproccors, (cop0 - System Control Coproccessor, cop2 - GTE), one 15 multiplier/divider, 32 general registers, one ALU, one shifter, one 16 address adder, 4kb of Instuction Cache, 1 kb of Data cache and NO floating 17 point unit. 18 19 Registers 20 ------------------------------------------------------------- 21 All registers are 32 bits wide. 22 23 0 zero Constant, always 0 24 1 at Assembler temporary. 25 2- 3 v0-v1 Subroutine return values 26 4- 7 a0-a3 Subroutine arguments 27 8-15 t0-t7 Temporaries, may be changed by subroutines 28 16-23 s0-s7 Register variables, must be saved by subs. 29 24-25 t8-t9 Temporaries, may be changed by subroutines 30 26-27 k0-k1 Reserved for the kernel 31 28 gp Global pointer 32 29 sp Stack pointer 33 30 fp(s8) 9th register variable, subs can use this as a frame 34 pointer 35 31 ra Return address 36 37 - pc Program counter 38 - hi,lo Registers of the multiplier/divider. 39 40 All registers behave the same, remarks are not hardware bound, but general 41 programming good practice. Respect these for compatability, especially if 42 you intend to use kernel routines. 43 Exceptions are register 0, and 31. Zero will always return 0, regardless 44 of any writing attempts. Ra is used by the normal jal instruction for the 45 return address. (points to the second instruction after the jal). Note that 46 the jalr instruction can use any register for the return address, though 47 usually only register 31 is used. 48 49 The PC is not really a register, and should not be seen like one. Hi, Lo 50 are the registers which the multiplier/divider returns its results to. 51 Special instructions are implemented to deal with them. 52 53 ------------------------------------------------------------- 54 Instructions 55 ------------------------------------------------------------- 56 rt target register (cpu general register 0-31) 57 rs source register (cpu general register 0-31) 58 rd destination register (cpu general register 0-31) 59 base base register (cpu general register 0-31) 60 imm 16 bit immediate 61 b? immediate value of ? bits wide. 62 c0r Coprocessor 0 register 63 c2d Coprocessor 2 (GTE) data register 64 c2c Coprocessor 2 (GTE) control register 65 66 67 imm(base) means an address of the value in the register + the immediate 68 value. 69 70 inst instruction name. 71 d number of instructions to wait before using r1 (target reg). 72 args format of the operand fields. 73 desc. description of the instruction. 74 75 76 inst d args desc. 77 78 *Load/Store instructions 79 80 lb 1 rt,imm(base) loads lowest byte of rt with addressed byte and 81 extends sign. 82 lbu 1 rt,imm(base) loads lowest byte of rt with addressed byte. 83 lh 1 rt,imm(base) loads lowest halfword of rt with addressed halfword 84 and extends sign. 85 lhu 1 rt,imm(base) loads lowest halfword of rt with addressed halfword. 86 lw 1 rt,imm(base) loads r1 with addressed word. 87 lwl 0 rt,imm(base) loads high order byte of rt with addressed byte and 88 then loads up to the low order word boundary into rt. 89 lwr 0 rt,imm(base) loads low order byte of rt with addressed byte and 90 then loads up to the high order word boundary into 91 rt. 92 93 There's no delay for lwl and lwr, so you can use them 94 directly following eachother. fe. to load a word 95 anywhere in memory without regard to alignment: 96 lwl a0,$0003(t0) 97 lwr a0,$0000(t0) 98 99 sb 1 rt,imm(base) stores lowest byte of rt in addressed byte. 100 sh 1 rt,imm(base) stores lowest halfword of rt in addressed halfword. 101 sw 1 rt,imm(base) stores rt in addressed word. 102 swl 0 rt,imm(base) unaligned store, see lwl 103 swr 0 rt,imm(base) unaligned store, see lwr 104 105 lui 0 rt,imm loads rt with immediate<<$10 106 107 *arithmic instructions 108 109 When an arithmic overflow occurs, rd will not be modified. 110 111 add 0 rd,rs,rt Adds rt to rs and stores the result in rd. 112 addu 0 rd,rs,rt Adds rt to rs, ignores arithmic overflow and stores 113 result in rd. 114 sub 0 rd,rs,rt Substracts rt from rs and stores result in rd. 115 subu 0 rd,rs,rt Substracts rt from rs, ignores arithmic overflow and 116 stores result in rd. 117 118 addi 0 rd,rs,imm Adds signextended immediate to rs, and stores the 119 result in rd. 120 addiu 0 rd,rs,imm Adds signextended immediate to rs, ignores arithmic 121 overflow and stores the result in rd. 122 123 subi 0 rd,rs,imm Substracts signextended immediate from rs and stores 124 the result in rd. 125 subiu 0 rd,rs,imm Substracts signextended immediate from rs, ignores 126 arithmic overflow, and stores the result in rd. 127 128 mult rs,rt Multiplies rs with rt, and stores the 64 bit sign 129 extended result in hi/lo. 130 multu rs,rt Multiplies rs with rt, and stores the 64 bit result 131 in hi/lo. 132 div rs,rt Divides rs by rt, and stores the quotient into lo, 133 and the remainder into high. Results are sign 134 extended. 135 divu rs,rt Divides rs by rt, and stores the quotient into lo, 136 and the remainder into high. 137 138 139 *logical instructions 140 141 and 0 rd,rs,rt Performs a bit wise AND between rs and rt, and 142 stores the result in rd. 143 or 0 rd,rs,rt Performs a bit wise OR between rs and rt, and 144 stores the result in rd. 145 xor 0 rd,rs,rt Performs a bit wise XOR between rs and rt, and 146 stores the result in rd. 147 nor 0 rd,rs,rt Performs a bit wise NOR between rs and rt, and 148 stores the result in rd. 149 150 andi 0 rd,rs,imm Performs a bit wise AND between rs and unsigned 151 immediate and stores the result in rd. 152 ori 0 rd,rs,imm Performs a bit wise OR between rs and unsigned 153 immediate and stores the result in rd. 154 xori 0 rd,rs,imm Performs a bit wise XOR between rs and unsigned 155 immediate and stores the result in rd. 156 157 *shifting instructions 158 159 sllv 0 rd,rs,rt Shifts rs rt bits to the left and stores the result 160 in rd. 161 srlv 0 rd,rs,rt Shifts rs rt bits to the right and stores the result 162 in rd. 163 srav 0 rd,rs,rt Shifts the value in rs rt bits to the right, 164 preserving sign, and stores the value in rd. 165 166 167 sll 0 rd,rs,b5 Shifts rs b5 bits to the left and stores the result 168 in rd. 169 srl 0 rd,rs,b5 Shifts rs b5 bits to the right and stores the result 170 in rd. 171 sra 0 rd,rs,b5 Shifts rs b5 bits to the right, preserving sign and 172 stores the result in rd. 173 174 *comparison instructions. 175 176 slt 0 rd,rs,rt rd=1 if rs < rt, else rd = 0 177 sltu 0 rd,rs,rt rd=1 if (unsigned)rs <(unsigned)rt, else rd = 0 178 179 slti 0 rd,rs,imm rd=1 if rs < imm, else rd = 0 180 sltiu 0 rd,rs,imm rd=1 if (unsigned)rs < (unsigned)imm, else rd = 0 181 182 *jumps and branches 183 184 Note the the instruction following the branch will always be executed. 185 186 j target jumps to target 187 jal target jumps to target and stores pc+8 into RA (second 188 instruction after the jal instruction) 189 190 jr rd jumps to address in rd 191 jalr (rt,) rd jumps to address in rd and stores pc+8 into RA, or 192 in rt. 193 194 beq rs,rt,imm branches to imm if rs == rt 195 bne rs,rt,imm branches to imm if rs != rt 196 197 bgtz rs,imm branches to imm if rs > 0 198 bltz rs,imm branches to imm if rs < 0 199 blez rs,imm branches to imm if rs <= 0 200 bgez rs,imm branches to imm if rs >= 0 201 bltzal rs,imm branches to imm and stores pc+8 into RA if rs < 0 202 bgezal rs,imm branches to imm rd and stores pc+8 into RA if rs >= 0 203 204 *system instructions 205 206 mfhi 2 rd moves HI into rd 207 mflo 2 rd moves LO into rd 208 mthi 2 rs moves rs into HI 209 mtlo 2 rs moves rs into LO 210 211 mtc0 2 rs,c0r moves rs into cop0 register c0r 212 mfc0 2 rd,c0r moves cop0 register c0r into rd 213 214 mtc2 2 rs,c2d moves rs into cop2 data register c2d 215 mfc2 2 rd,c2d moves cop2 data register c2d into rd 216 217 ctc2 2 rs,c2c moves rs into cop2 control register c2d 218 cfc2 2 rd,c2c moves cop2 control register c2d into rd 219 220 lwc2 1 c2d,imm(base) load cop2 data register with addressed word 221 swc2 1 c2d,imm(base) stores cop2 data register at addressed word 222 223 syscall (b20) generates a system call exception 224 break (b20) generates a breakpoint exception 225 the 20bits wide code field is not passed, but 226 must be read from the instuction itself if you 227 want to use it. 228 229 cop2 b25 Coprocessor operation is started. b25 is 230 passed as parameter. 231 232 rfe restores the interrupt enable and kernel 233 previlege bits. 234 235 tlb instructions see MIPS doc. 236 237 -------------------------------------------------------------------------- 238 Cop0 - System control coprocessor 239 -------------------------------------------------------------------------- 240 241 Registers: 242 # Name rw Desciption. 243 244 ------------------------------------------------------------- 245 16 ERREG 246 ------------------------------------------------------------- 247 15 PRid r COP0 type and rev level 248 bit |31 16|15 8|7 0| 249 desc| |Imp |Rev | 250 251 Imp 3 CP0 type R3000A 252 7 IDT unique (3041) use REV to determine correct 253 config. 254 Rev Revision level. 255 ------------------------------------------------------------- 256 14 EPC r Return address from trap 257 258 Contains the return address after an exception. This address is 259 the instruction at which the exception took place, unless BD is 260 set in CAUSE, when the instruction is EPC+4. 261 ------------------------------------------------------------- 262 13 CAUSE r Describes the most recently recognised exception 263 bit |31|30|29 28|27 26 25 24 23 22 21 20 19 18 17 16| 264 desc|BD| 0|CE | 0| 265 bit |15 14 13 12 11 10 09 08|07|06 05 04 03 02|01 00| 266 desc|Ip | 0|Excode | 0| 267 268 BD Is set when last exception points to the 269 branch instuction instead of the instruction 270 in the branch delay slot, where the exception 271 occurred. 272 CE Contains the coprocessor number if the exception 273 occurred because of a coprocessor instuction for 274 a coprocessor which wasn't enabled in SR. 275 Ip Interrupt pending field. Bit 8 and 9 are RW, and 276 contain the last value written to them. As long 277 as any of the bits are set they will cause an 278 interrupt if the corresponding bit is set in IM. 279 Excode Describes what kind of exception occured: 280 0 INT Interrupt 281 1 MOD Tlb modification 282 2 TLBL Tlb load 283 3 TLBS Tlb store 284 4 AdEL Address error, load/I-fetch 285 5 AdES Address error, store 286 The address errors occur when attempting to read 287 outside of KUseg in user mode and when the address 288 is misaligned. 289 6 IBE Bus error on Instruction fetch. 290 7 DBE Bus error on Data load. 291 8 Syscall Generated unconditionally by at syscall instruction 292 9 BP Breakpoint - break instruction. 293 10 RI Reserved instruction 294 11 CpU Coprocessor unusable 295 12 Ov Arithmic overflow 296 ------------------------------------------------------------- 297 12 SR rw System status register 298 bit |31 |30 |29 |28 |27 26|25|24 23|22 |21|20|19|18|17 |16 | 299 desc|CU3|CU2|CU1|CU0| 0|RE| 0|BEV|TS|PE|CM|PZ|SwC|IsC| 300 301 bit |15 14 13 12 11 10 09 08|07 06|05 |04 |03 |02 |01 |00 | 302 desc|Im | 0|KUo|IEo|KUp|IEp|KUc|IEc| 303 304 CUx 0 Coprocessor x disabled 305 1 Coprocessor x enabled 306 CU2 is for the GTE, CU1 is for the FPA, which is 307 not available in the PSX. 308 CU0 0 Cop0 in kernal mode. 309 1 Cop0 in user mode. 310 Makes some nominally privileged instruction usable 311 in user mode. Normal instructions are usable regardless 312 of this bit's setting. 313 RE 0 Normal 'endianness' 314 1 Reverse 'endianness' 315 Reverses the byte order in which data is stored in 316 memory. (lo-hi -> hi-lo) 317 BEV 0 Boot exception vectors in RAM 318 1 Boot exception vectors in ROM (kseg1) 319 TS TLB shutdown. Gets set if a programm address simultaniously 320 matches 2 TLB entries. 321 PE Cache parity error. Does not cause exception. 322 CM Shows the result of the last load operation with the D-cache 323 isolated. It gets set if the cache really contained data 324 for the addressed memory location. 325 PZ When set cache parity bits are written as 0. 326 Isc 0 Do not isolate cache. 327 1 Isolate cache. All load and store operations are targetted 328 to the Data cache, and never the main memory. 329 Swc 0 Normal cache mode. 330 1 Swapped cache mode. I cache will act as D cache and vice 331 versa. Use only with Isc to access & invalidate i cache 332 entries 333 Im 8 bit interrupt mask fields. When set the corresponding 334 interrupts are allowed to cause an exception. 335 KUc 0 User mode privilege , rfe pops KUp here 336 1 Kernal mode privilege 337 IEc 0 Interrupts enabled , rfe pops IUp here 338 1 All interrupts disabled. 339 KUp KUc gets pushed here on an exception, rfe pops KUo here 340 IUp IUc gets pushed here on an exception, rfe pops IUo here 341 KUo KUp gets pushed here on an exception 342 IUo IUp gets pushed here on an exception 343 ------------------------------------------------------------- 344 11 BPCM rw Execute breakpoint mask. 345 346 Program counter is ANDed with this value and then compared to 347 the value in BPC. 348 ------------------------------------------------------------- 349 10 TLBHI/PID 350 ------------------------------------------------------------- 351 9 BDAM rw Data Access breakpoint mask. 352 353 Data fetch address is ANDed with this value and then compared 354 to the value in BDA 355 ------------------------------------------------------------- 356 8 BadVaddr r Bad Virtual Address. 357 358 Contains the address whose reference caused an exception. Set 359 on any MMU type of exceptions, on references outside of kuseg 360 and on any misaligned reference. 361 ------------------------------------------------------------- 362 7 DCIC rw Breakpoint control 363 |1f 1e 1d 1c|1b|1a|19|18|17|16 15 14 13 12 11 10||0f 00| 364 | 1 1 1 0| W| R|DA|PC| 1| 0| 0| 365 366 W 0 367 1 Break on Write 368 R 0 369 1 Break on Read 370 DA 0 Data access breakpoint disabled 371 1 Data access breakpoint enabled 372 PC 0 Execution breakpoint disabled 373 1 Execution breakpoint enabled 374 375 To use the Execution breakpoint, set PC. To use the Data access 376 breakpoint set DA and either R, W or both. Both breakpoints 377 can be used simultaniously. When a breakpoint occurs the PSX 378 jumps to $00000040. 379 ------------------------------------------------------------- 380 6 PIDMASK 381 ------------------------------------------------------------- 382 5 BDA rw Breakpoint on data access. 383 384 Sets the breakpoint address for load/store operations 385 ------------------------------------------------------------- 386 4 CTXT 387 ------------------------------------------------------------- 388 3 BPC rw Breakpoint on execute. 389 390 Sets the breakpoint address to break on on execute. 391 ------------------------------------------------------------- 392 2 TLBLO 393 1 RAND 394 0 INX 395 396 For TLB details see mips doc. 397 398 -------------------------------------------------------------------------- 399 PC file server 400 -------------------------------------------------------------------------- 401 Caetla supports pcdrv: device, the SN systems device extension to access 402 files on the drive of the pc. This fileserver can be accessed by using the 403 kernel functions, with the 'pcdrv:' device name prefix to the filenames or 404 using the SN system calls. 405 406 ------------------------------------------------------------- 407 SN System calls 408 ------------------------------------------------------------- 409 The following SN system calls for the fileserver are provided. 410 Accessed by setting the registers and using the break command 411 with the specified field. 412 ------------------------------------------------------------- 413 PCInit Inits the fileserver. 414 break $0101 415 ------------------------------------------------------------- 416 PCCreat Creates a new file on PC. 417 break $0102 418 in: a1 pointer to file name 419 a2 file attribute 420 out: v0 0 = success, -1 = failure 421 v1 file handle or error code if v0 is negative 422 ------------------------------------------------------------- 423 PCOpen Opens a file on the PC. 424 break $0103 425 in: a1 pointer to file name 426 a2 access mode 0 read only 427 1 write only 428 2 r/w 429 out: v0 0 = succes, -1 = failure 430 v1 file handle or error code if v0 is negative 431 ------------------------------------------------------------- 432 PCClose Closes a file on the PC. 433 break $0104 434 in: a1 file handle 435 out: v0 0 = succes, -1 = failure 436 v1 0 = succes, error code if v0 is negative 437 ------------------------------------------------------------- 438 PCRead Reads from an open file on PC. 439 break $0105 440 in: a1 file handle 441 a2 length in bytes 442 a3 pointer to store address 443 out: v0 0 = succes, -1 = failure 444 v1 number of read bytes or error code if v0 is 445 negative. 446 447 Note: Does not stop at eof, so if you set more bytes to read 448 than the filelength, the fileserver will pad with zero 449 bytes. If you are not sure of the the filelength obtain 450 the filelength by PClSeek (a2 = 0, a3 = 2, v1 will return 451 the length of the file, don't forget to reset the file 452 pointer to the start before calling PCread!) 453 ------------------------------------------------------------- 454 PCWrite Writes to an open file on PC. 455 break $0106 456 in: a1 file handle 457 a2 length in bytes 458 a3 pointer to read address 459 out: v0 0 = succes, -1 = failure 460 v1 number of written bytes or error code if v0 461 is negative. 462 ------------------------------------------------------------- 463 PClSeek Repositions the file pointer 464 break $0107 465 in: a1 file handle 466 a2 number of bytes to move. 467 a3 position from 0 Beginning of file 468 1 Current pointer 469 2 End of file 470 out: v0 0 = succes, -1 = failure 471 v1 file pointer 472 ------------------------------------------------------------- 473 Attributes are passed as is. File attributes for the pc file 474 system are like this: 475 bit | 7 6| 5| 4| 3| 2| 1| 0| 476 desc| 0| A| D| 0| S| H| R| 477 478 A Archive file 479 D Directory 480 S System file 481 H Hidden file 482 R Read only file 483 ------------------------------------------------------------- 484 485 486 -------------------------------------------------------------------------- 487 System calls 488 -------------------------------------------------------------------------- 489 Kernel system calls are accessed by loading the call number in t1, and 490 jumping to the specifeed address. 491 A0 call $3f means: load t1 with $3f and jump to $000000a0. 492 493 ------------------------------------------------------------- 494 Printf Print string to console. 495 A0 call $3f 496 in: a0 Pointer to 0 terminated string. 497 a1-a3 Arguments. 498 sp+$10 499 500 Prints the specified string to the console (ie. pc screen). 501 String can contain standard C escape sequences and conversion 502 characters, except the floating point types (%e, %f, %g). 503 Variables are passed in a1 to a3. More variables are passed at 504 sp+$10. 505 ------------------------------------------------------------- 506 openevent adds an event structure to the event table. 507 B0 call $08 508 in: a0 Event class. 509 a1 Event spec. 510 a2 Event mode. 511 a3 Address of function to be executed when 512 event occurs. 513 out: v0 Event descriptor, -1 if failed. 514 515 Opens an event, should be called within a critical section. 516 The return value is used to identify the event to the other 517 even functions. 518 A list of event classes, specs and modes is at the end of this 519 section. 520 ------------------------------------------------------------- 521 closeevent releases an event structure from the 522 B0 call $09 event table. 523 in: a0 Event descriptor. 524 out: v0 1 on success, 0 if failed. 525 ------------------------------------------------------------- 526 enableevent Turns on event handling for specified event. 527 B0 call $0c 528 in: a0 Event descriptor. 529 out: v0 1 on success, 0 if failed. 530 ------------------------------------------------------------- 531 disableevent Turns off event handling for specified event. 532 B0 call $0d 533 in: a0 Event descriptor. 534 out: v0 1 on success, 0 if failed. 535 ------------------------------------------------------------- 536 open Opens a file for IO. 537 B0 call $32 538 in: a0 File name, terminated with 0 539 a1 Access mode 540 out: v0 File handle, or -1 if error. 541 542 Opens a file on the target device for io. Access mode is set 543 like this: 544 545 bit 0 1 = Read 546 1 1 = Write 547 9 1 = New file 548 15 1 = Asynchronous mode? 549 16-31 Number of memory card blocks for a new file on the 550 memory card. 551 552 The PSX can have a maximum of 16 files open at any time. 553 ------------------------------------------------------------- 554 lseek Move the file pointer. 555 B0 call $33 556 in: a0 File handle 557 a1 Movement offset in bytes 558 a2 0 = from start of file 559 1 = from current file pointer 560 2 = Bugs. Should be from end of file. 561 562 Moves the file pointer the number of bytes in a1, relative to 563 the location specified by a2. Movement from the eof is incorrect. 564 Also, movement beyond the end of the file is not checked. 565 ------------------------------------------------------------- 566 read Read data from an open file. 567 B0 call $34 568 in: a0 File Handle 569 a1 Pointer to address to store read data 570 a2 Number of bytes to read 571 out: v0 Number of bytes actually read, -1 if failed. 572 573 Reads the number of bytes from the specified open file. If length 574 is not specified an error is returned. Read per $0080 bytes from 575 memory card (bu:) and per $0800 from cdrom (cdrom:). 576 ------------------------------------------------------------- 577 write Write data to an open file. 578 B0 call $35 579 in: a0 File handle 580 a1 Pointer to adress to read data from. 581 a2 Number of bytes to write. 582 out: v0 Number of bytes written. 583 584 Writes the number of bytes to the specified open file. Write 585 to the memory card per $0080 bytes. Writing to the cdrom returns 0. 586 ------------------------------------------------------------- 587 close Close an open file. 588 B0 call $36 589 in: a0 File handle 590 out: v0 File hande if success, -1 if failed. 591 ------------------------------------------------------------- 592 cd Change the current directory on target device. 593 B0 call $40 594 in: a0 Pointer to new directory path 595 out: v0 1 if success, 0 if failed. 596 597 Changes the current directory on target system. 598 ------------------------------------------------------------- 599 firstfile Finds the first file to match the name. 600 B0 call $42 601 in: a0 Pointer to the file name. 602 a1 Pointer to direntry structure. 603 out: v0 0 if unsuccessfull, else same as a1. 604 605 Searches for the first file to match the name in the string 606 pointed to by a0. Wildcards (?, *) may be used. Start the name 607 with the device you want to address. (ie. pcdrv:) Different 608 drives can be accessed as normally by their drive names (a:, c:) 609 if path is omitted after the device, the current directory will 610 be used. 611 612 A direntry structure looks like this: 613 614 $00 - $13 db Filename, terminated with 0. 615 $14 dw File attribute 616 $18 dw File size 617 $1c dw Pointer to next direntry 618 $20 - $27 db Reserved by system 619 ------------------------------------------------------------- 620 nextfile Searches for the next file to match the name. 621 B0 call $43 622 in: a0 Pointer to direntry structure 623 out: v0 0 if unsuccesful, else same as a0. 624 625 Uses the settings of a previous firstfile command. 626 ------------------------------------------------------------- 627 rename Rename a file on target device. 628 B0 call $44 629 in: a0 Pointer to old file name 630 a1 Pointer to new file name 631 out: v0 1 if successful, 0 if failed. 632 ------------------------------------------------------------- 633 delete Delete a file on target device. 634 B0 call $45 635 in: a0 Pointer to file name 636 out: v0 1 if successful, 0 if failed. 637 ------------------------------------------------------------- 638 639 Event Classes 640 641 The upper byte of each event type, is a descriptor byte, which 642 identifies the type of event to kernal routines. 643 644 Descriptors: 645 $ff Thread 646 $f0 Hardware 647 $f1 Event 648 $f2 Root counter 649 $f3 User event 650 $f4 BIOS 651 652 Hardware events: 653 $f0000001 VBLANK 654 $f0000002 GPU 655 $f0000003 CDROM Decoder 656 $f0000004 DMA controller 657 $f0000005 RTC0 658 $f0000006 RTC1 659 $f0000007 RTC2 660 $f0000008 Controller 661 $f0000009 SPU 662 $f000000a PIO 663 $f000000b SIO 664 $f0000010 Exception 665 $f0000011 memory card 666 $f0000012 memory card 667 $f0000013 memory card 668 669 Root counter events: 670 $f2000000 counter 0 (pixel clock) 671 $f2000001 counter 1 (horizontal retrace) 672 $f2000002 counter 2 (one-eighth of system clock) 673 $f2000003 counter 3 (vertical retrace) 674 675 Bios events: 676 $f4000001 memory card 677 $f4000002 libmath 678 679 Event Specs: 680 $0001 counter becomes zero 681 $0002 interrupted 682 $0004 end of i/o 683 $0008 file was closed 684 $0010 command acknowledged 685 $0020 command completed 686 $0040 data ready 687 $0080 data end 688 $0100 time out 689 $0200 unknown command 690 $0400 end of read buffer 691 $0800 end of write buffer 692 $1000 general interrupt 693 $2000 new device 694 $4000 system call instruction 695 $8000 error happned 696 $8001 previous write error happned 697 $0301 domain error in libmath 698 $0302 range error in libmath 699 700 Event modes: 701 $1000 Handle on interrupt 702 $2000 Do not handle on interrupt. 703 704 -------------------------------------------------------------------------- 705 Root Counters 706 -------------------------------------------------------------------------- 707 There are 4 root counters. 708 709 Counter Base address Synced to 710 0 $1f801100 pixelclock 711 1 $1f801110 horizontal retrace 712 2 $1f801120 1/8 system clock 713 3 vertical retrace 714 715 Each have three registers, one with the current value, one with the counter 716 mode, and one with a target value. 717 718 ------------------------------------------------------------- 719 $11x0 Count r 720 bit |31 16|15 0| 721 desc|Garbage |Count | 722 723 Count Current count value, 0-$ffff 724 725 Upper word seems to contain only garbage. 726 ------------------------------------------------------------- 727 $11x4 Mode rw 728 bit |31 10|9 |8 |7 |6 |5 |4 |3 | 2 1| 0| 729 desc|Garbage |Div|Clc| |Iq2| |Iq1|Tar| |En| 730 731 En 0 Counter running 732 1 Counter stopped (only counter 2) 733 Tar 0 Count to $ffff 734 1 Count to value in target register 735 Iq1 Set both for IRQ on target reached. 736 Iq2 737 Clc 0 System clock (it seems) 738 1 Pixel clock (counter 0) 739 Horizontal retrace (counter 1) 740 Div 0 System clock (it seems) 741 1 1/8 * System clock (counter 2) 742 743 When Clc and Div of the counters are zero, they all run at the 744 same speed. This speed seems to be about 8 times the normal 745 speed of root counter 2, which is specified as 1/8 the system 746 clock. 747 748 Bits 10 to 31 seem to contain only garbage. 749 ------------------------------------------------------------- 750 $11x8 Target rw 751 bit |31 16|15 0| 752 desc|Garbage? |Target | 753 754 Target Target value, 0-$ffff 755 756 Upper word seems to contain only garbage. 757 ------------------------------------------------------------- 758 Quick step-by-step: 759 760 To set up an interrupt using these counters you can do the following: 761 1 - Reset the counter. (Mode = 0) 762 2 - Set its target value, set mode. 763 3 - Enable corresponding bit in the interrupt mask register ($1f801074) 764 bit 3 = Counter 3 (Vblank) 765 bit 4 = Counter 0 (System clock) 766 bit 5 = Counter 1 (Hor retrace) 767 bit 6 = Counter 2 (Pixel) 768 4 - Open an event. (Openevent bios call - $b0, $08) 769 With following arguments: 770 a0-Rootcounter event descriptor or'd with the counter number. 771 ($f2000000 - counter 0, $f2000001 - counter 1,$f2000002 - counter 2, 772 $f2000003 - counter 3) 773 a1-Spec = $0002 - interrupt event. 774 a2-Mode = Interrupt handling ($1000) 775 a3-Pointer to your routine to be excuted. 776 The return value in V0 is the event identifier. 777 778 5 - Enable the event, with the corresponding bioscall ($b0,$0c) with 779 the identifier as argument. 780 781 6 - Make sure interrupts are enabled. (Bit 0 and bit 10 of the COP0 status 782 register must be set.) 783 784 Your handler just has to restore the registers it uses, and it should 785 terminate with a normal jr ra. 786 787 To turn off the interrupt, first call disable event ($b0, $0d) and then 788 close it using the Close event call ($b0,$09) both with the event number 789 as argument. 790 791 -------------------------------------------------------------------------- 792 DMA 793 -------------------------------------------------------------------------- 794 795 ------------------------------------------------------------- 796 DPCR Dma control register $1f8010f0 797 |1f 1c|1b 18|17 14|13 10|0f 0c|0b 08|07 04|03 00| 798 | |Dma6 |Dma5 |Dma4 |Dma3 |Dma2 |Dma1 |Dma0 | 799 800 Each register has a 4 bit control block allocated in this 801 register. 802 Bit 3: 1= Dma Enabled 803 2: ? 804 1: ? 805 0: ? 806 807 Bit 3 must be set for a channel to operate. 808 ------------------------------------------------------------- 809 DICR Dma interrupt register $1f8010f4 810 811 ------------------------------------------------------------- 812 The DMA channel registers are located starting at $1f801080. The 813 base adress for each channel is: 814 $1f801080 DMA channel 0 MDECin 815 $1f801090 DMA channel 1 MDECout 816 $1f8010a0 DMA channel 2 GPU (lists + image data) 817 $1f8010b0 DMA channel 3 CDrom 818 $1f8010c0 DMA channel 4 SPU 819 $1f8010d0 DMA channel 5 PIO 820 $1f8010e0 DMA channel 6 OTC (reverse clear OT) 821 822 ------------------------------------------------------------- 823 D_MADR DMA base address. $1f8010x0 824 bit |1f 00| 825 desc|madr | 826 827 madr pointer to the adress the DMA will start reading 828 from/writing to 829 ------------------------------------------------------------- 830 D_BCR DMA block control $1f8010x4 831 bit |1f 10|0f 00| 832 desc|ba |bs | 833 834 ba Amount of blocks 835 bs Blocksize (words) 836 837 The channel will transfer ba blocks of bs words. Take care 838 not to set the size larger than the buffer of the corresponding 839 unit can hold. (GPU & SPU both have a $10 word buffer). A 840 larger blocksize, means a faster transfer. 841 ------------------------------------------------------------- 842 D_CHCR DMA channel control $1f8010x8 843 bit |1f-19|18|17-0c|0b|0a|09|08|07 01|00| 844 desc| 0|Tr| 0| 0|Li|Co| 0| 0|Dr| 845 846 Tr 0 No DMA transfer busy. 847 1 Start DMA transfer/DMA transfer busy. 848 Li 1 Transfer linked list. (GPU only) 849 Co 1 Transfer continous stream of data. 850 Dr 0 direction to memory 851 1 direction from memory 852 ------------------------------------------------------------- 853 854 -------------------------------------------------------------------------- 855 doomed@c64.org <- corrections/additions latest update -> psx.rules.org 856 -------------------------------------------------------------------------- 857 16/may/1999 Initial version. 858 19/may/1999 Added Breakpoint info. <Herozero> 859 3/jun/1999 Root counters, some stuff on events and DMA added. 860 861 (thanx to ppl in <>) 862 -------------------------------------------------------------------------- 863 thanx & hello to the usual. 864 865