cpu.h (1145B)
1 #pragma once 2 3 #include "interconnect.h" 4 #include "types.h" 5 6 typedef struct { 7 u32 _0; 8 u32 fn; 9 u32 t; 10 u32 s; 11 u32 d; 12 u32 imm; 13 u32 imm_se; 14 u32 imm_jump; 15 u32 sub; 16 u32 shift; 17 u32 cop_opcode; 18 } instruction; 19 20 typedef struct { 21 u32 _0; 22 u32 _1; 23 } Load; 24 25 typedef struct { 26 /* Program Counter register */ 27 u32 pc; 28 /* Cop0 register 12: Status Register*/ 29 u32 next_pc; 30 u32 current_pc; 31 u32 cause; 32 u32 epc; 33 u32 sr; 34 u32 hi; 35 u32 lo; 36 u32 branch; 37 u32 delay_slot; 38 instruction next_instruction; 39 Interconnect* inter; 40 /* General Registers */ 41 u32 regs[32]; 42 /* Second set of regs to emulate the LOAD DELAY SLOT. 43 They contain the output of the current instruction */ 44 u32 out_regs[32]; 45 /* LOAD -> on load delay slots */ 46 Load load; 47 } CPU; 48 49 typedef enum { 50 E_SYSCALL = 0x8, 51 E_BREAK = 0x9, 52 E_LOAD_ADRESS_ERROR = 0x4, 53 E_STORE_ADRESS_ERROR = 0x5, 54 E_COPROCESSOR_ERROR = 0xb, 55 E_ILLEGAL_INSTRUCTION = 0xa, 56 E_OVERFLOW = 0xc 57 } EXCEPTION; 58 59 CPU* new_cpu(Interconnect*); 60 u32 CPU_load32(CPU*, u32); 61 void CPU_decode_and_execute(CPU*, instruction*); 62 void CPU_run_next_instruction(CPU*); 63 64 instruction new_instr(u32); 65 void print_instr(instruction*);