gpu.h (3768B)
1 #pragma once 2 3 #include "types.h" 4 #include "sr.h" 5 6 typedef enum _GP0_MODE { 7 GP0_MODE_COMMAND, 8 GP0_MODE_IMAGE_LOAD 9 } GP0_MODE; 10 11 typedef enum _TEXTURE_DEPTH { 12 TD_T4BIT, 13 TD_T8BIT, 14 TD_T15BIT 15 } TEXTURE_DEPTH; 16 17 typedef enum _FIELD { 18 F_TOP, 19 F_BOTTOM 20 } FIELD; 21 22 typedef enum _DMA_DIRECTION { 23 DMA_DIR_OFF, 24 DMA_DIR_FIFO, 25 DMA_DIR_CPUTOGP0, 26 DMA_DIR_VRAMTOCPU 27 } DMA_DIRECTION; 28 29 typedef enum _VMODE { 30 VMODE_NTSC, 31 VMODE_PAL 32 } VMODE; 33 34 typedef enum _DISPLAY_DEPTH { 35 DISP_DEPTH_D15BITS, 36 DISP_DEPTH_D24BITS 37 } DISPLAY_DEPTH; 38 39 typedef struct _GPU_CMD_BUFFER { 40 u32 buffer[12]; 41 u32 len; 42 } GPU_CMD_BUFFER; 43 44 /* line 1045 in no$psx docs */ 45 typedef struct _GPU { 46 u8 page_base_x; 47 u8 page_base_y; 48 u8 semi_transparency; 49 TEXTURE_DEPTH texture_depth; 50 u8 dithering; 51 u8 draw_to_display; 52 u8 force_set_mask_bit; 53 u8 preserve_masked_pixels; 54 FIELD field; 55 u8 texture_disable; 56 u8 hres; 57 u8 vres; 58 VMODE vmode; 59 DISPLAY_DEPTH display_depth; 60 u8 interlaced; 61 u8 display_disabled; 62 u8 interrupt; 63 DMA_DIRECTION dma_direction; 64 65 u8 rectangle_texture_x_flip; 66 u8 rectangle_texture_y_flip; 67 68 u8 texture_window_x_mask; 69 u8 texture_window_y_mask; 70 u8 texture_window_x_offset; 71 u8 texture_window_y_offset; 72 u16 drawing_area_left; 73 u16 drawing_area_top; 74 u16 drawing_area_right; 75 u16 drawing_area_bottom; 76 i16 drawing_x_offset; 77 i16 drawing_y_offset; 78 u16 display_vram_x_start; 79 u16 display_vram_y_start; 80 u16 display_horiz_start; 81 u16 display_horiz_end; 82 u16 display_line_start; 83 u16 display_line_end; 84 85 GP0_MODE gp0_mode; 86 87 GPU_CMD_BUFFER gp0_command; 88 u32 gp0_words_remaining; 89 void (*gp0_command_method) (struct _GPU*); 90 91 REN* ren; 92 } GPU; 93 94 /* GPU */ 95 static inline u8 HOR_RES_from_fields(u8 hr1, u8 hr2) { return (hr2 & 1) | ((hr1 & 3) << 1); } 96 static inline u32 HOR_RES_into_status(u8 hr) {return ((u32)hr) << 16; } 97 void GPU_gp1(GPU*, u32); 98 void GPU_gp1_reset(GPU*, u32); /* GP1(0x00): Reset */ 99 void GPU_gp1_reset_command_buffer(GPU*, u32); /* GP1(0x01): Reset Command Buffer */ 100 void GPU_gp1_acknowledge_irq(GPU*, u32); /* GP1(0x02): Acknoweledge Interrupt */ 101 void GPU_gp1_display_enable(GPU*, u32); /* GP1(0x03): Display Enable */ 102 void GPU_gp1_dma_direction(GPU*, u32); /* GP1(0x04): DMA Direction */ 103 void GPU_gp1_display_mode(GPU*, u32); /* GP1(0x08): Display Mode */ 104 void GPU_gp1_display_vram_start(GPU*, u32); /* GP1(0x05): Display VRAM start */ 105 void GPU_gp1_display_horizontal_range(GPU*, u32); /* GP1(0x06): Display Horizontal Range */ 106 void GPU_gp1_display_vertical_range(GPU*, u32); /* GP1(0x07): Display Vertical Range */ 107 108 /* GP0 */ 109 void GPU_gp0(GPU*, u32); 110 void GPU_gp0_nop(GPU*); 111 void GPU_gp0_clear_cache(GPU*); /* GP0(0x01): Clear Cache */ 112 void GPU_gp0_image_load(GPU*); /* GP0(0xa0): Image Load */ 113 void GPU_gp0_draw_mode(GPU*); 114 void GPU_gp0_drawing_area_top_left(GPU*); /* GP0(0xe3): Set Drawing Area top left */ 115 void GPU_gp0_drawing_area_bottom_right(GPU*); /* GP0(0xe4): Set Drawing Area bottom right */ 116 void GPU_gp0_drawing_offset(GPU*); /* GP0(0xe5): Set Drawing Offset */ 117 void GPU_gp0_texture_window(GPU*); /* GP0(0xe2): Set Texture Window */ 118 void GPU_gp0_mask_bit_setting(GPU*); /* GP0(0xe6): Set Mask Bit Setting */ 119 void GPU_gp0_quad_mono_opaque(GPU*); /* GP0(0x28): Monochrome Opaque Quadrilateral */ 120 void GPU_gp0_triangle_shaded_opaque(GPU*); /* GP0(0x30): Shaded Opaque Triangle */ 121 void GPU_gp0_quad_shaded_opaque(GPU*); /* GP0(0x38): Shaded Opaque Quadrilateral */ 122 void GPU_gp0_quad_texture_blend_opaque(GPU*); /* GP0(0x2c): Textured Opaque Quadrilateral */ 123 void GPU_gp0_image_store(GPU*); /* GP0(0xc0): Image store */ 124 GPU* GPU_new(void); 125 u32 GPU_status(GPU*); 126 u32 GPU_read(GPU*); 127 128 /* GPU's Command Buffer: GPU_CMD_BUFFER */ 129 GPU_CMD_BUFFER* GPU_CMD_BUFFER_new(void); 130 void GPU_CMD_BUFFER_clear(GPU_CMD_BUFFER*); 131 void GPU_CMD_BUFFER_push_word(GPU_CMD_BUFFER*, u32);