mem.h (1574B)
1 #pragma once 2 3 #include "util.h" 4 #include "types.h" 5 6 typedef enum e_Direction { 7 DIR_TO_RAM, 8 DIR_FROM_RAM 9 } Direction; 10 11 typedef enum e_Step { 12 STEP_INCREMENT, 13 STEP_DECREMENT 14 } Step; 15 16 typedef enum e_Sync { 17 SYNC_MANUAL, 18 SYNC_REQUEST, 19 SYNC_LINKED_LIST 20 } Sync; 21 22 typedef enum e_Port { 23 PORT_MDEC_IN = 0, 24 PORT_MDEC_OUT = 1, 25 PORT_GPU = 2, 26 PORT_CD_ROM = 3, 27 PORT_SPU = 4, 28 PORT_PIO = 5, 29 PORT_OTC = 6, 30 PORT_INVALID = 7 31 } Port; 32 33 typedef struct RAM { 34 u8* data; 35 } RAM; 36 37 typedef struct Channel { 38 u8 enable; 39 Direction direction; 40 Step step; 41 Sync sync; 42 u32 base; 43 u8 trigger; 44 u8 chop; 45 u8 chop_dma_sz; 46 u8 chop_cpu_sz; 47 u8 dummy; 48 u16 block_size; 49 u16 block_count; 50 } Channel; 51 52 typedef struct DMA { 53 u32 control; 54 u8 irq_en; 55 u8 channel_irq_en; 56 u8 channel_irq_flags; 57 u8 force_irq; 58 u8 irq_dummy; 59 Channel channels[7]; 60 } DMA; 61 62 63 DMA* DMA_new(void); 64 u32 DMA_control(DMA*); 65 void DMA_set_control(DMA*, u32); 66 u8 DMA_irq(DMA*); 67 u32 DMA_interrupt(DMA*); 68 void DMA_set_interrupt(DMA*, u32); 69 Channel* DMA_channel(DMA*, Port); 70 71 Channel* CHANNEL_new(void); 72 u32 CHANNEL_control(Channel*); 73 void CHANNEL_set_control(Channel*, u32); 74 u32 CHANNEL_base(Channel*); 75 void CHANNEL_set_base(Channel*, u32); 76 u32 CHANNEL_block_control(Channel*); 77 void CHANNEL_set_block_control(Channel*, u32); 78 u8 CHANNEL_active(Channel*); 79 u8 CHANNEL_transfer_size(Channel*, u32*); 80 void CHANNEL_done(Channel*); 81 82 RAM* RAM_new(void); 83 u8 RAM_load8(RAM*, u32); 84 u16 RAM_load16(RAM*, u32); 85 u32 RAM_load32(RAM*, u32); 86 void RAM_store8(RAM* r, u32, u8); 87 void RAM_store16(RAM* r, u32, u16); 88 void RAM_store32(RAM* r, u32, u32);