tags (12804B)
1 BIOS bios.h /^struct BIOS {$/ 2 BIOS_load32 bios.c /^BIOS_load32(BIOS* b, u32 offset)$/ 3 BIOS_load8 bios.c /^u8 BIOS_load8(BIOS* b, u32 offset) { return b->dat/ 4 BIOS_new bios.c /^BIOS_new(const char* path)$/ 5 Bool tags /^Bool tags \/^Bool types.h \\\/^typedef uint8_t Bo/ 6 C sr.h /^typedef struct {u8 b;u8 g;u8 r;} C;$/ 7 CDROM cdrom.h /^}CDROM;$/ 8 CDROM_Fifo cdrom.h /^} CDROM_Fifo;$/ 9 CDROM_Fifo_is_empty cdrom.c /^CDROM_Fifo_is_empty(CDROM_Fifo fifo)$/ 10 CDROM_Fifo_is_full cdrom.c /^CDROM_Fifo_is_full(CDROM_Fifo fifo)$/ 11 CDROM_new cdrom.c /^CDROM_new()$/ 12 CDROM_store8 cdrom.c /^CDROM_store8(CDROM* cd, u32 off, u8 val)$/ 13 CDROM_write cdrom.c /^void CDROM_write(u32 offset, u8 val)$/ 14 CHANNEL_active mem.c /^CHANNEL_active(Channel* ch)$/ 15 CHANNEL_base mem.c /^CHANNEL_base(Channel* ch)$/ 16 CHANNEL_block_control mem.c /^CHANNEL_block_control(Channel* ch)$/ 17 CHANNEL_control mem.c /^CHANNEL_control(Channel* ch)$/ 18 CHANNEL_done mem.c /^CHANNEL_done(Channel* ch)$/ 19 CHANNEL_new mem.c /^CHANNEL_new(void)$/ 20 CHANNEL_set_base mem.c /^CHANNEL_set_base(Channel* ch, u32 val)$/ 21 CHANNEL_set_block_control mem.c /^CHANNEL_set_block_control(Channel* ch, u32 val)$/ 22 CHANNEL_set_control mem.c /^CHANNEL_set_control(Channel* ch, u32 val)$/ 23 CHANNEL_transfer_size mem.c /^CHANNEL_transfer_size(Channel* ch, u32 *res)$/ 24 COLOR_from_gp0 sr.c /^COLOR_from_gp0(u32 val)$/ 25 CPU cpu.h /^} CPU;$/ 26 CPU_decode_and_execute cpu.c /^CPU_decode_and_execute(CPU* cpu, instruction* i)$/ 27 CPU_load16 cpu.c /^u16 CPU_load16(CPU* cpu, u32 addr) { return INTER_/ 28 CPU_load32 cpu.c /^u32 CPU_load32(CPU* cpu, u32 addr) { return INTER_/ 29 CPU_load8 cpu.c /^u8 CPU_load8(CPU* cpu, u32 addr) { return INTER_lo/ 30 CPU_run_next_instruction cpu.c /^CPU_run_next_instruction(CPU* cpu)$/ 31 CPU_store16 cpu.c /^void CPU_store16(CPU* cpu, u32 addr, u16 val) { IN/ 32 CPU_store32 cpu.c /^void CPU_store32(CPU* cpu, u32 addr, u32 val) { IN/ 33 CPU_store8 cpu.c /^void CPU_store8(CPU* cpu, u32 addr, u8 val) { IN/ 34 C_SWAP sr.h /^#define C_SWAP(x, y) { C temp = x; x = y; y = temp/ 35 C_new sr.c /^C_new(u32 b)$/ 36 Channel mem.h /^} Channel;$/ 37 DISPLAY_DEPTH gpu.h /^} DISPLAY_DEPTH;$/ 38 DMA mem.h /^} DMA;$/ 39 DMA_DIRECTION gpu.h /^} DMA_DIRECTION;$/ 40 DMA_control mem.c /^DMA_control(DMA* dma)$/ 41 DMA_interrupt mem.c /^DMA_interrupt(DMA* dma)$/ 42 DMA_irq mem.c /^DMA_irq(DMA* dma)$/ 43 DMA_new mem.c /^DMA_new(void)$/ 44 DMA_set_control mem.c /^DMA_set_control(DMA* dma, u32 val)$/ 45 DMA_set_interrupt mem.c /^DMA_set_interrupt(DMA* dma, u32 val)$/ 46 Direction mem.h /^} Direction;$/ 47 EXCEPTION cpu.h /^} EXCEPTION;$/ 48 FB_flip_vert sr.c /^FB_flip_vert(u32 *data)$/ 49 FIELD gpu.h /^} FIELD;$/ 50 GP0_MODE gpu.h /^} GP0_MODE;$/ 51 GPU gpu.h /^} GPU;$/ 52 GPU_CMD_BUFFER gpu.h /^} GPU_CMD_BUFFER;$/ 53 GPU_CMD_BUFFER_clear gpu.c /^GPU_CMD_BUFFER_clear(GPU_CMD_BUFFER* cmd_buffer)$/ 54 GPU_CMD_BUFFER_new gpu.c /^GPU_CMD_BUFFER_new(void)$/ 55 GPU_CMD_BUFFER_push_word gpu.c /^GPU_CMD_BUFFER_push_word(GPU_CMD_BUFFER* cmd_buffe/ 56 GPU_LOG defs.h /^#define GPU_LOG(fmt, ...) \\$/ 57 GPU_gp0 gpu.c /^GPU_gp0(GPU* gpu, u32 val)$/ 58 GPU_gp0_clear_cache gpu.c /^void GPU_gp0_clear_cache(GPU* gpu) { \/* Not imple/ 59 GPU_gp0_draw_mode gpu.c /^GPU_gp0_draw_mode(GPU* gpu)$/ 60 GPU_gp0_drawing_area_bottom_right gpu.c /^GPU_gp0_drawing_area_bottom_right(GPU* gpu)$/ 61 GPU_gp0_drawing_area_top_left gpu.c /^GPU_gp0_drawing_area_top_left(GPU* gpu)$/ 62 GPU_gp0_drawing_offset gpu.c /^GPU_gp0_drawing_offset(GPU* gpu)$/ 63 GPU_gp0_image_load gpu.c /^GPU_gp0_image_load(GPU* gpu)$/ 64 GPU_gp0_image_store gpu.c /^GPU_gp0_image_store(GPU* gpu)$/ 65 GPU_gp0_mask_bit_setting gpu.c /^GPU_gp0_mask_bit_setting(GPU* gpu)$/ 66 GPU_gp0_nop gpu.c /^void GPU_gp0_nop(GPU* gpu) {}$/ 67 GPU_gp0_quad_mono_opaque gpu.c /^GPU_gp0_quad_mono_opaque(GPU* gpu)$/ 68 GPU_gp0_quad_shaded_opaque gpu.c /^GPU_gp0_quad_shaded_opaque(GPU* gpu)$/ 69 GPU_gp0_quad_texture_blend_opaque gpu.c /^GPU_gp0_quad_texture_blend_opaque(GPU* gpu)$/ 70 GPU_gp0_texture_window gpu.c /^GPU_gp0_texture_window(GPU* gpu)$/ 71 GPU_gp0_triangle_shaded_opaque gpu.c /^GPU_gp0_triangle_shaded_opaque(GPU* gpu)$/ 72 GPU_gp1 gpu.c /^GPU_gp1(GPU* gpu, u32 val)$/ 73 GPU_gp1_acknowledge_irq gpu.c /^GPU_gp1_acknowledge_irq(GPU* gpu, u32 val)$/ 74 GPU_gp1_display_enable gpu.c /^GPU_gp1_display_enable(GPU* gpu, u32 val)$/ 75 GPU_gp1_display_horizontal_range gpu.c /^GPU_gp1_display_horizontal_range(GPU* gpu, u32 val/ 76 GPU_gp1_display_mode gpu.c /^GPU_gp1_display_mode(GPU* gpu, u32 val)$/ 77 GPU_gp1_display_vertical_range gpu.c /^GPU_gp1_display_vertical_range(GPU* gpu, u32 val)$/ 78 GPU_gp1_display_vram_start gpu.c /^GPU_gp1_display_vram_start(GPU* gpu, u32 val)$/ 79 GPU_gp1_dma_direction gpu.c /^GPU_gp1_dma_direction(GPU* gpu, u32 val)$/ 80 GPU_gp1_reset gpu.c /^GPU_gp1_reset(GPU* gpu, u32 val)$/ 81 GPU_gp1_reset_command_buffer gpu.c /^GPU_gp1_reset_command_buffer(GPU* gpu, u32 val)$/ 82 GPU_new gpu.c /^GPU_new(void)$/ 83 GPU_read gpu.c /^GPU_read(GPU* gpu)$/ 84 GPU_status gpu.c /^GPU_status(GPU* gpu)$/ 85 HOR_RES_from_fields gpu.c /^u8 HOR_RES_from_fields(u8 hr1, u8 hr2) { return (/ 86 HOR_RES_into_status gpu.c /^u32 HOR_RES_into_status(u8 hr) {return ((u32)hr) </ 87 INTER_dma_reg interconnect.c /^INTER_dma_reg(Interconnect* inter, u32 offset)$/ 88 INTER_do_dma interconnect.c /^INTER_do_dma(Interconnect* inter, Port port)$/ 89 INTER_do_dma_block interconnect.c /^INTER_do_dma_block(Interconnect* inter, Port port)/ 90 INTER_do_dma_linked_list interconnect.c /^INTER_do_dma_linked_list(Interconnect* inter, Port/ 91 INTER_load16 interconnect.c /^INTER_load16(Interconnect* inter, u32 addr)$/ 92 INTER_load32 interconnect.c /^INTER_load32(Interconnect* inter, u32 addr)$/ 93 INTER_load8 interconnect.c /^INTER_load8(Interconnect* inter, u32 addr)$/ 94 INTER_set_dma_reg interconnect.c /^INTER_set_dma_reg(Interconnect* inter, u32 offset,/ 95 INTER_store16 interconnect.c /^INTER_store16(Interconnect* inter, u32 addr, u16 v/ 96 INTER_store32 interconnect.c /^INTER_store32(Interconnect* inter, u32 addr, u32 v/ 97 INTER_store8 interconnect.c /^INTER_store8(Interconnect* inter, u32 addr, u8 val/ 98 IVEC2_op sr.c /^IVEC2_op(ivec2 a, ivec2 b, enum mop mop)$/ 99 IVEC2_ops sr.c /^IVEC2_ops(ivec2 a, i32 b, enum mop mop)$/ 100 I_SWAP sr.h /^#define I_SWAP(x, y) { int temp = x; x = y; y = te/ 101 Interconnect interconnect.h /^struct Interconnect {$/ 102 LOG defs.h /^#define LOG(level, fmt, ...) \\$/ 103 LOG_ERR defs.h /^#define LOG_ERR(x) fprintf(stderr, (x))$/ 104 Load cpu.h /^} Load;$/ 105 Mmain main.c /^main(int argc, char **argv)$/ 106 POSITION_from_gp0 sr.c /^POSITION_from_gp0(u32 val)$/ 107 Port mem.h /^} Port;$/ 108 RAM mem.h /^} RAM;$/ 109 RAM_load16 mem.c /^RAM_load16(RAM* r, u32 offset)$/ 110 RAM_load32 mem.c /^RAM_load32(RAM* r, u32 offset)$/ 111 RAM_load8 mem.c /^RAM_load8(RAM* r, u32 offset)$/ 112 RAM_new mem.c /^RAM_new(void) $/ 113 RAM_store16 mem.c /^RAM_store16(RAM* r, u32 offset, u16 val)$/ 114 RAM_store32 mem.c /^RAM_store32(RAM* r, u32 offset, u32 val)$/ 115 RAM_store8 mem.c /^RAM_store8(RAM* r, u32 offset, u8 val)$/ 116 REN sr.h /^} REN;$/ 117 REN_FB_set sr.c /^void REN_FB_set(REN* ren, i32 x, i32 y, u8 r, u8 g/ 118 REN_display sr.c /^REN_display(REN* ren)$/ 119 REN_draw sr.c /^REN_draw(REN* ren)$/ 120 REN_flush sr.c /^REN_flush(REN* ren) {$/ 121 REN_new sr.c /^REN_new()$/ 122 REN_push_quad sr.c /^REN_push_quad(REN* ren, ivec2 verts[4], C colors[4/ 123 REN_push_triangle sr.c /^REN_push_triangle(REN* ren, ivec2 verts[3], C colo/ 124 REN_triangle sr.c /^REN_triangle(REN* ren, ivec2 verts[3], C colors[3]/ 125 SHADERS_gradient_shader shaders.c /^SHADERS_gradient_shader(float alpha, float beta, f/ 126 Step mem.h /^} Step;$/ 127 Sync mem.h /^} Sync;$/ 128 TEXTURE_DEPTH gpu.h /^} TEXTURE_DEPTH;$/ 129 UTIL_contains util.c /^UTIL_contains(u32 start, u32 length, u32 addr, u32/ 130 VEC2I_SWAP sr.h /^#define VEC2I_SWAP(x, y) { ivec2 temp = x; x = y; / 131 VMODE gpu.h /^} VMODE;$/ 132 branch cpu.c /^branch(CPU* cpu, u32 offset)$/ 133 checked_addi32 util.c /^checked_addi32(i32 a, i32 b, i32* res)$/ 134 checked_subi32 util.c /^checked_subi32(i32 a, i32 b, i32* res)$/ 135 draw_scanline sr.c /^draw_scanline(REN* ren, int y, int x1, C c1, int x/ 136 exception cpu.c /^exception(CPU* cpu, EXCEPTION cause)$/ 137 i16 types.h /^typedef int16_t i16;$/ 138 i32 types.h /^typedef int32_t i32;$/ 139 i64 types.h /^typedef int64_t i64;$/ 140 i8 types.h /^typedef int8_t i8;$/ 141 instruction cpu.h /^} instruction;$/ 142 ivec2 sr.h /^typedef struct { int x, y; } ivec2;$/ 143 mask_region util.c /^u32 mask_region(u32 addr) { return addr & REGION_M/ 144 mop sr.h /^enum mop {ADD, SUB, MUL, DIV};$/ 145 new_cpu cpu.c /^new_cpu(Interconnect* inter) {$/ 146 new_instr cpu.c /^new_instr(u32 i)$/ 147 new_interconnect interconnect.c /^new_interconnect(void) {$/ 148 op_add cpu.c /^op_add(CPU* cpu, instruction* i)$/ 149 op_addi cpu.c /^op_addi(CPU* cpu, instruction* i)$/ 150 op_addiu cpu.c /^op_addiu(CPU* cpu, instruction* i)$/ 151 op_addu cpu.c /^op_addu(CPU* cpu, instruction* i)$/ 152 op_and cpu.c /^op_and(CPU* cpu, instruction* i)$/ 153 op_andi cpu.c /^op_andi(CPU* cpu, instruction *i)$/ 154 op_beq cpu.c /^op_beq(CPU* cpu, instruction* i)$/ 155 op_bgtz cpu.c /^op_bgtz(CPU* cpu, instruction* i)$/ 156 op_blez cpu.c /^op_blez(CPU* cpu, instruction* i)$/ 157 op_bne cpu.c /^op_bne(CPU* cpu, instruction* i)$/ 158 op_break cpu.c /^op_break(CPU* cpu, instruction* i)$/ 159 op_bxx cpu.c /^op_bxx(CPU* cpu, instruction* i)$/ 160 op_cop0 cpu.c /^op_cop0(CPU* cpu, instruction* i)$/ 161 op_cop1 cpu.c /^op_cop1(CPU* cpu, instruction* i)$/ 162 op_cop2 cpu.c /^op_cop2(CPU* cpu, instruction* i)$/ 163 op_cop3 cpu.c /^op_cop3(CPU* cpu, instruction* i)$/ 164 op_div cpu.c /^op_div(CPU* cpu, instruction* i)$/ 165 op_divu cpu.c /^op_divu(CPU* cpu, instruction* i)$/ 166 op_illegal cpu.c /^op_illegal(CPU* cpu, instruction* i)$/ 167 op_j cpu.c /^op_j(CPU* cpu, instruction* i)$/ 168 op_jal cpu.c /^op_jal(CPU* cpu, instruction* i) $/ 169 op_jalr cpu.c /^void op_jalr(CPU* cpu, instruction* i) $/ 170 op_jr cpu.c /^op_jr(CPU* cpu, instruction* i) $/ 171 op_lb cpu.c /^op_lb(CPU* cpu, instruction* i)$/ 172 op_lbu cpu.c /^op_lbu(CPU* cpu, instruction* i)$/ 173 op_lh cpu.c /^op_lh(CPU* cpu, instruction* i)$/ 174 op_lhu cpu.c /^op_lhu(CPU* cpu, instruction* i)$/ 175 op_lui cpu.c /^op_lui(CPU* cpu, instruction* i)$/ 176 op_lw cpu.c /^op_lw(CPU* cpu, instruction* i)$/ 177 op_lwc0 cpu.c /^void op_lwc0(CPU* cpu, instruction* i) { exception/ 178 op_lwc1 cpu.c /^void op_lwc1(CPU* cpu, instruction* i) { exception/ 179 op_lwc2 cpu.c /^void op_lwc2(CPU* cpu, instruction* i) { fprintf(s/ 180 op_lwc3 cpu.c /^void op_lwc3(CPU* cpu, instruction* i) { exception/ 181 op_lwl cpu.c /^op_lwl(CPU* cpu, instruction* i)$/ 182 op_lwr cpu.c /^op_lwr(CPU* cpu, instruction* i)$/ 183 op_mfc0 cpu.c /^op_mfc0(CPU* cpu, instruction* i)$/ 184 op_mfhi cpu.c /^op_mfhi(CPU* cpu, instruction* i)$/ 185 op_mflo cpu.c /^op_mflo(CPU* cpu, instruction* i)$/ 186 op_mtc0 cpu.c /^op_mtc0(CPU* cpu, instruction* i)$/ 187 op_mthi cpu.c /^op_mthi(CPU* cpu, instruction* i)$/ 188 op_mtlo cpu.c /^op_mtlo(CPU* cpu, instruction* i)$/ 189 op_mult cpu.c /^op_mult(CPU* cpu, instruction* i)$/ 190 op_multu cpu.c /^op_multu(CPU* cpu, instruction* i)$/ 191 op_nor cpu.c /^op_nor(CPU* cpu, instruction* i)$/ 192 op_or cpu.c /^op_or(CPU* cpu, instruction* i)$/ 193 op_ori cpu.c /^op_ori(CPU* cpu, instruction* i)$/ 194 op_rfe cpu.c /^op_rfe(CPU* cpu, instruction* i)$/ 195 op_sb cpu.c /^op_sb(CPU* cpu, instruction* i)$/ 196 op_sh cpu.c /^op_sh(CPU* cpu, instruction* i)$/ 197 op_sll cpu.c /^op_sll(CPU* cpu, instruction* i)$/ 198 op_sllv cpu.c /^op_sllv(CPU* cpu, instruction* i)$/ 199 op_slt cpu.c /^op_slt(CPU* cpu, instruction* i)$/ 200 op_slti cpu.c /^op_slti(CPU* cpu, instruction* i)$/ 201 op_sltiu cpu.c /^op_sltiu(CPU* cpu, instruction* i)$/ 202 op_sltu cpu.c /^op_sltu(CPU* cpu, instruction* i)$/ 203 op_sra cpu.c /^op_sra(CPU* cpu, instruction* i)$/ 204 op_srav cpu.c /^op_srav(CPU* cpu, instruction* i)$/ 205 op_srl cpu.c /^op_srl(CPU* cpu, instruction* i)$/ 206 op_srlv cpu.c /^op_srlv(CPU* cpu, instruction* i)$/ 207 op_sub cpu.c /^op_sub(CPU* cpu, instruction* i)$/ 208 op_subu cpu.c /^op_subu(CPU* cpu, instruction* i)$/ 209 op_sw cpu.c /^op_sw(CPU* cpu, instruction* i)$/ 210 op_swc0 cpu.c /^void op_swc0(CPU* cpu, instruction* i) { exception/ 211 op_swc1 cpu.c /^void op_swc1(CPU* cpu, instruction* i) { exception/ 212 op_swc2 cpu.c /^void op_swc2(CPU* cpu, instruction* i) { fprintf(s/ 213 op_swc3 cpu.c /^void op_swc3(CPU* cpu, instruction* i) { exception/ 214 op_swl cpu.c /^op_swl(CPU* cpu, instruction* i)$/ 215 op_swr cpu.c /^op_swr(CPU* cpu, instruction* i)$/ 216 op_syscall cpu.c /^void op_syscall(CPU* cpu, instruction* i)$/ 217 op_xor cpu.c /^op_xor(CPU* cpu, instruction* i)$/ 218 op_xori cpu.c /^op_xori(CPU* cpu, instruction* i)$/ 219 point sr.h /^typedef struct { double x, y, z; } point;$/ 220 reg cpu.c /^u32 reg(CPU* cpu, u32 reg) { return cpu->out_regs[/ 221 set_reg cpu.c /^void set_reg(CPU* cpu, u32 reg, u32 val) { cpu->ou/ 222 swap_color util.c /^swap_color(C *a, C *b) { C temp = *a; *a = *b; *b / 223 swap_int util.c /^swap_int(int *a, int *b) { int temp = *a; *a = *b;/ 224 swap_vec2 util.c /^swap_vec2(ivec2 *a, ivec2 *b) { ivec2 temp = *a; */ 225 u16 types.h /^typedef uint16_t u16;$/ 226 u32 types.h /^typedef uint32_t u32;$/ 227 u64 types.h /^typedef uint64_t u64;$/ 228 u8 types.h /^typedef uint8_t u8;$/ 229 vec3f sr.h /^typedef struct { double x, y, z; } vec3f;$/