commit dd25e590a2a1f91dd5a6ea1023d96546cb0aef74
parent b5095fb6afc35d83145bfe8f303904e81784d822
Author: root <root@fif>
Date: Sat, 27 Apr 2024 16:53:38 +0000
Macro for printing and gpu source files
Diffstat:
5 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/build.sh b/build.sh
@@ -1 +1 @@
-c++ -Wall -Wpedantic -static -Wall -pedantic -g src/*.c -o bin/ultimecia
+c++ -O3 -Wall -Wpedantic -static -Wall -pedantic -g src/*.c -o bin/ultimecia
diff --git a/src/defs.h b/src/defs.h
@@ -4,4 +4,4 @@
#define PANIC(...) do { fprintf(stderr, __VA_ARGS__); exit(EXIT_FAILURE); } while(0)
-// #define DEBUG 1;
+#define DEBUG 1;
diff --git a/src/gpu.c b/src/gpu.c
@@ -0,0 +1 @@
+
diff --git a/src/gpu.h b/src/gpu.h
@@ -0,0 +1,33 @@
+#pragma once
+
+typedef struct _GPU {
+ u8 page_base_x;
+ u8 page_base_y;
+ u8 semi_transparency;
+ TEXTURE_DEPTH texture_depth;
+ u8 dithering;
+ u8 draw_to_display;
+ u8 force_set_mask_bit;
+ u8 preserve_masked_pixels;
+ FIELD field;
+ u8 texture_disable;
+ u8 hres;
+ u8 vres;
+ VMODE vmode;
+ DISPLAY_DEPTH diplay_depth;
+ u8 interlaced;
+ u8 display_disabled;
+ u8 interrupt;
+ DMA_DIRECTION dma_direction;
+} GPU;
+
+typdef enum _TEXTURE_DEPTH {
+ TD_T4BIT,
+ TD_T8BIT,
+ TD_T15BIT,
+} TEXTURE_DEPTH;
+
+typedef enum _FIELD {
+ F_TOP,
+ F_BOTTOM,
+} FIELD;
diff --git a/src/interconnect.c b/src/interconnect.c
@@ -44,7 +44,9 @@ INTER_load8(Interconnect* inter, u32 addr)
contains = UTIL_contains(IRQ_CONTROL_START, IRQ_CONTROL_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
printf("IRQ CONTROL read %08X\n", offset);
+#endif
return 0;
}
@@ -72,7 +74,9 @@ INTER_load16(Interconnect* inter, u32 addr)
contains = UTIL_contains(SPU_START, SPU_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stderr, "Unhandled read from SPU register: %08X\n", offset);
+#endif
return 0;
}
@@ -83,7 +87,9 @@ INTER_load16(Interconnect* inter, u32 addr)
contains = UTIL_contains(IRQ_CONTROL_START, IRQ_CONTROL_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
printf("IRQ CONTROL read %08X\n", offset);
+#endif
return 0;
}
@@ -119,14 +125,18 @@ INTER_load32(Interconnect* inter, u32 addr)
contains = UTIL_contains(IRQ_CONTROL_START, IRQ_CONTROL_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
printf("IRQ CONTROL read %08X\n", offset);
+#endif
return 0;
}
contains = UTIL_contains(TIMERS_START, TIMERS_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
printf("TIMERS read %08X\n", offset);
+#endif
return 0;
}
@@ -139,7 +149,9 @@ INTER_load32(Interconnect* inter, u32 addr)
contains = UTIL_contains(GPU_START, GPU_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
printf("GPU read %08X\n", abs_addr);
+#endif
switch(offset)
{
@@ -165,7 +177,9 @@ INTER_store8(Interconnect* inter, u32 addr, u8 val)
contains = UTIL_contains(EXPANSION2_START, EXPANSION2_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "Ignoring write to EXPANSION2 register at: %08X\n", abs_addr);
+#endif
return;
}
@@ -199,14 +213,18 @@ INTER_store16(Interconnect* inter, u32 addr, u16 val)
contains = UTIL_contains(SPU_START, SPU_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "Ignoring SPU register write: %X\n", abs_addr);
+#endif
return;
}
contains = UTIL_contains(TIMERS_START, TIMERS_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "Ignoring TIMER register write to offset: %X\n", offset);
+#endif
return;
}
@@ -220,7 +238,9 @@ INTER_store16(Interconnect* inter, u32 addr, u16 val)
contains = UTIL_contains(IRQ_CONTROL_START, IRQ_CONTROL_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
printf("IRQ control write %08X at address %08X\n", val, offset);
+#endif
return;
}
@@ -238,8 +258,11 @@ INTER_store32(Interconnect* inter, u32 addr, u32 val)
contains = 0;
abs_addr = mask_region(addr);
- if (addr % 4 != 0)
+ if (addr % 4 != 0) {
+#ifndef DEBUG
fprintf(stderr, "Unaligned_store32_address: %08X", addr);
+#endif
+ }
contains = UTIL_contains(RAM_START, RAM_SIZE, abs_addr, &offset);
if (contains)
@@ -251,21 +274,27 @@ INTER_store32(Interconnect* inter, u32 addr, u32 val)
contains = UTIL_contains(RAM_SIZE_START, RAM_SIZE_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "Ignoring RAM_SIZE register write %X\n", abs_addr);
+#endif
return;
}
contains = UTIL_contains(CACHECONTROL_START, CACHECONTROL_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "Ignoring CACHECONTROL abs_address write: %X\n", abs_addr);
+#endif
return;
}
contains = UTIL_contains(IRQ_CONTROL_START, IRQ_CONTROL_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "Ignoring IRQ CONTROL write %08X to address %08X\n", val, offset);
+#endif
return;
}
@@ -279,14 +308,18 @@ INTER_store32(Interconnect* inter, u32 addr, u32 val)
contains = UTIL_contains(TIMERS_START, TIMERS_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "TIMER register write %08X to offset: %08X\n", val, offset);
+#endif
return;
}
contains = UTIL_contains(GPU_START, GPU_SIZE, abs_addr, &offset);
if (contains)
{
+#ifndef DEBUG
fprintf(stdout, "GPU write %08X to address %08X\n", val, offset);
+#endif
return;
}
@@ -307,7 +340,9 @@ INTER_store32(Interconnect* inter, u32 addr, u32 val)
}
break;
default:
+#ifndef DEBUG
fprintf(stderr, "Unhandled write to SYSCONTROL register\n");
+#endif
return;
}
return;
@@ -449,7 +484,9 @@ INTER_do_dma_block(Interconnect* inter, Port port)
src_word = RAM_load32(inter->ram, cur_addr);
switch(port) {
case PORT_GPU:
+#ifndef DEBUG
printf("GPU data %08X\n", src_word);
+#endif
break;
default:
fprintf(stderr, "Unhandled DMA destination port: %d", (u8)port);
@@ -506,7 +543,9 @@ INTER_do_dma_linked_list(Interconnect* inter, Port port)
while (remsz > 0) {
addr = (addr + 4) & 0x1ffffc;
command = RAM_load32(inter->ram, addr);
+#ifndef DEBUG
printf("GPU command %08X\n", command);
+#endif
remsz--;
}
